# L78L05ABD13TR

**STMicroelectronics** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8

L78L05ABD13TR from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VOUT | power_out | Regulated 5 V output (4.6 V min / 5.4 V max at TJ=25 °C). Up to 100 mA with adequate heat-sinking. Recommend 0.1 µF ceramic to GND for stability. |
| 2 | GND | power_in | Ground reference. On the SO-8 package pins 2, 3, 6 and 7 are internally commoned to the die attach flag to lower thermal resistance; tie all four to the ground plane for best heat spreading. |
| 3 | GND | power_in | Ground reference. Internally commoned with pins 2, 6 and 7 to the die attach flag for thermal spreading; connect all four to the ground plane. |
| 4 | NC | unconnected | Not connected. Leave floating or tie to ground; no internal bond. |
| 5 | NC | unconnected | Not connected. Leave floating or tie to ground; no internal bond. |
| 6 | GND | power_in | Ground reference. Internally commoned with pins 2, 3 and 7 to the die attach flag for thermal spreading; connect all four to the ground plane. |
| 7 | GND | power_in | Ground reference. Internally commoned with pins 2, 3 and 6 to the die attach flag for thermal spreading; connect all four to the ground plane. |
| 8 | VIN | power_in | Unregulated DC input. Absolute maximum 30 V for the 5 V output variant; typical dropout ~2 V so VIN ≥ ~7 V for full 5 V regulation. Recommend 0.33 µF ceramic to GND close to the pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | PMIC |
| Pins | 8 |

## Ordering variants

Same part, different packaging or reel option.

- `L78L05ABD13TRD`
- `L78L05ABD13TR`
- `L78L05ABD13TRZ`
- `L78L05ABD13TRAP`
- `L78L05ABD13TRZAP`

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output voltage (TJ = 25 °C) | VO | 4.8 | 5 | 5.2 | V | TJ = 25 °C | 16 |
| Output voltage (IO = 1 to 40 mA) | VO | 4.75 |  | 5.25 | V | IO = 1 to 40 mA, VI = 7 to 20 V | 16 |
| Output voltage (IO = 1 to 70 mA) | VO | 4.75 |  | 5.25 | V | IO = 1 to 70 mA, VI = 10 V | 16 |
| Line regulation | ∆VO |  |  | 150 | mV | VI = 7.3 to 20 V, TJ = 25 °C | 16 |
| Line regulation | ∆VO |  |  | 100 | mV | VI = 8 to 20 V, TJ = 25 °C | 16 |
| Load regulation | ∆VO |  |  | 60 | mV | IO = 1 to 100 mA, TJ = 25 °C | 16 |
| Load regulation | ∆VO |  |  | 30 | mV | IO = 1 to 40 mA, TJ = 25 °C | 16 |
| Quiescent current | Id |  |  | 6 | mA | TJ = 25 °C | 16 |
| Quiescent current | Id |  |  | 5.5 | mA | TJ = 125 °C | 16 |
| Quiescent current change | ∆Id |  |  | 0.1 | mA | IO = 1 to 40 mA | 16 |
| Quiescent current change | ∆Id |  |  | 1.5 | mA | VI = 8 to 20 V | 16 |
| Output noise voltage | eN |  |  | 40 | µV | B = 10 Hz to 100 kHz, TJ = 25 °C | 16 |
| Supply voltage rejection | SVR | 41 | 49 |  | dB | VI = 8 to 18 V, f = 120 Hz; IO = 40 mA, TJ = 25 °C | 16 |
| Dropout voltage | Vd |  |  | 2 | V |  | 16 |
| DC input voltage (VO = 3.3 to 9 V) | VI |  |  | 30 | V | VO = 3.3 to 9 V | 5 |
| Output current | IO |  |  | 100 | mA |  | 5 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 5 |
| Operating junction temperature range (L78LxxAB) | TOP | -40 |  | 125 | °C | for L78LxxAB | 5 |
| Thermal resistance junction-case (SO-8) | RthJC |  |  | 20 | °C/W |  | 5 |
| Thermal resistance junction-ambient (SO-8) | RthJA |  |  | 55 | °C/W | Considering 6 cm² of copper board heat-sink | 5 |

## CAD (KiCad official)

- Symbol: `L78L05ABD13TR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `l78l05abd13tr-etched.step` / `l78l05abd13tr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l78l05abd13tr.step` / `l78l05abd13tr.glb` are the bare package body.

## 3D model downloads

Two STEP files. Same geometry, different body top:

| File | Size | Use it when |
|---|---|---|
| [`l78l05abd13tr.step`](l78l05abd13tr.step) | 122 KB | You want the bare part, or you mark your own boards. |
| [`l78l05abd13tr-etched.step`](l78l05abd13tr-etched.step) | 2.5 MB | You want the part with `L78L05ABD13TR` already on it. |

The marking in the etched file is real recessed geometry cut into the solid, not a
texture or a decal: 617 faces against 147 in the bare model. It
survives export, section views, and rendering in any CAD tool, and it drops straight
into KiCad or Fusion with no extra setup.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/l78l05abd13tr.pdf) (45 pp, sha256 `43922ae159face7e`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l78l05abd13tr-datasheet.pdf)