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L6986HTR

Public Made by Adom

by adom

STMicroelectronics DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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L6986HTR

STMicroelectronics · DC-DC Converters · HTSSOP-16-EP

L6986HTR from STMicroelectronics, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RST output The RST open-collector output is driven low when the output voltage is out of regulation and is released after the adjustable DELAY time once the output is over the active delay threshold.
2 VCC power_out Connect a ceramic capacitor (≥ 470 nF) to filter the internal voltage reference; this pin supplies the embedded analog circuitry, with absolute maximum VCC of -0.3 V to (VIN + 0.3 V) or 4 V max.
3 SS/INH bidirectional An open-collector stage can disable the device by clamping this pin to GND (INH mode), and an internal 4 µA typ. current generator charges the external capacitor to set the soft-start; absolute maximum is -0.3 V to VIN + 0.3 V.
4 SYNCH/ISKIP input In LNM this pin provides master/slave synchronization, and in LCM it selects the skip current level; leave it floating when not used in LNM.
5 FSW input A pull-up resistor (E24 series) to VCC or pull-down to GND selects the switching frequency, with the strapping active only before the soft-start phase.
6 MLF input A pull-up resistor (E24 series) to VCC or pull-down to GND selects low consumption mode or low noise mode and the active RST threshold, with the strapping active only before the soft-start phase.
7 COMP passive Output of the error amplifier, to which the designed compensation network is connected.
8 DELAY passive An external capacitor on this pin sets the delay before RST is released after the output passes the reset threshold; if left floating, RST behaves like a Power Good signal.
9 VOUT input Output voltage sensing input; absolute maximum rating is -0.3 V to 10 V.
10 SGND power_in Signal ground; must be connected to the exposed pad together with PGND.
11 PGND power_in Power ground; must be connected to SGND and the exposed pad.
12 PGND power_in Power ground; must be connected to SGND and the exposed pad.
13 LX output Switching node; absolute maximum rating is -0.3 V to VIN + 0.3 V, and the high-side and low-side switch current is limited to 2 A.
14 LX output Switching node; absolute maximum rating is -0.3 V to VIN + 0.3 V, and the high-side and low-side switch current is limited to 2 A.
15 VIN power_in DC input voltage; operating range is 4 V to 38 V with an absolute maximum of 40 V.
16 VBIAS power_in Typically connected to the regulated output voltage; an external voltage reference can supply part of the analog circuitry to improve light-load efficiency, and it should be connected to GND if not used (absolute maximum -0.3 V to (VIN + 0.3 V) or 6 V max).
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package HTSSOP-16-EP
Category Power Supply Chip
Pins 17

CAD (KiCad official)

  • Symbol: L6986HTR
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: l6986htr-etched.step / l6986htr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6986htr.step / l6986htr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (68 pp, sha256 b526b22bab1d8834, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF