component
L6986HTR
Public Made by Adomby adom
STMicroelectronics DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# L6986HTR++**STMicroelectronics** · DC-DC Converters · HTSSOP-16-EP++L6986HTR from STMicroelectronics, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RST | output | The RST open-collector output is driven low when the output voltage is out of regulation and is released after the adjustable DELAY time once the output is over the active delay threshold. |+| 2 | VCC | power_out | Connect a ceramic capacitor (≥ 470 nF) to filter the internal voltage reference; this pin supplies the embedded analog circuitry, with absolute maximum VCC of -0.3 V to (VIN + 0.3 V) or 4 V max. |+| 3 | SS/INH | bidirectional | An open-collector stage can disable the device by clamping this pin to GND (INH mode), and an internal 4 µA typ. current generator charges the external capacitor to set the soft-start; absolute maximum is -0.3 V to VIN + 0.3 V. |+| 4 | SYNCH/ISKIP | input | In LNM this pin provides master/slave synchronization, and in LCM it selects the skip current level; leave it floating when not used in LNM. |+| 5 | FSW | input | A pull-up resistor (E24 series) to VCC or pull-down to GND selects the switching frequency, with the strapping active only before the soft-start phase. |+| 6 | MLF | input | A pull-up resistor (E24 series) to VCC or pull-down to GND selects low consumption mode or low noise mode and the active RST threshold, with the strapping active only before the soft-start phase. |+| 7 | COMP | passive | Output of the error amplifier, to which the designed compensation network is connected. |+| 8 | DELAY | passive | An external capacitor on this pin sets the delay before RST is released after the output passes the reset threshold; if left floating, RST behaves like a Power Good signal. |+| 9 | VOUT | input | Output voltage sensing input; absolute maximum rating is -0.3 V to 10 V. |+| 10 | SGND | power_in | Signal ground; must be connected to the exposed pad together with PGND. |+| 11 | PGND | power_in | Power ground; must be connected to SGND and the exposed pad. |+| 12 | PGND | power_in | Power ground; must be connected to SGND and the exposed pad. |+| 13 | LX | output | Switching node; absolute maximum rating is -0.3 V to VIN + 0.3 V, and the high-side and low-side switch current is limited to 2 A. |+| 14 | LX | output | Switching node; absolute maximum rating is -0.3 V to VIN + 0.3 V, and the high-side and low-side switch current is limited to 2 A. |+| 15 | VIN | power_in | DC input voltage; operating range is 4 V to 38 V with an absolute maximum of 40 V. |+| 16 | VBIAS | power_in | Typically connected to the regulated output voltage; an external voltage reference can supply part of the analog circuitry to improve light-load efficiency, and it should be connected to GND if not used (absolute maximum -0.3 V to (VIN + 0.3 V) or 6 V max). |+| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | HTSSOP-16-EP |+| Category | Power Supply Chip |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `L6986HTR`+- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)+- 3D model files: `l6986htr-etched.step` / `l6986htr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l6986htr.step` / `l6986htr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589829662811074560) (68 pp, sha256 `b526b22bab1d8834`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/l6986htr-datasheet.pdf)
page.jsonadded+257@@ -0,0 +1,257 @@+{+ "slug": "l6986htr",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "l6986htr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "l6986htr.kicad_sym",+ "l6986htr.kicad_mod",+ "l6986htr.glb",+ "l6986htr.step",+ "l6986htr.lbr",+ "docs/hero.png",+ "docs/l6986htr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "l6986htr-hero.glb",+ "l6986htr-hero.overlay.json"+ ],+ "component": {+ "mpn": "L6986HTR",+ "manufacturer": "STMicroelectronics",+ "package": "HTSSOP-16-EP",+ "pin_count": 17,+ "category": "Power Supply Chip",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589829662811074560",+ "parts": {+ "symbol": "l6986htr.kicad_sym",+ "footprint": "l6986htr.kicad_mod",+ "model_3d": "l6986htr-hero.glb",+ "model_3d_plain": "l6986htr.glb",+ "model_3d_step": "l6986htr-etched.step",+ "model_3d_step_plain": "l6986htr.step",+ "lbr": "l6986htr.lbr"+ },+ "distributor_links": {+ "lcsc": "C2071414",+ "digikey": "497-19084-2-ND",+ "mouser": "511-L6986HTR"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:29:12Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "497-19084-2-ND",+ "status": "found",+ "lifecycle": "Last Time Buy"+ },+ "mouser": {+ "pn": "511-L6986HTR",+ "status": "found",+ "lifecycle": "End of Life"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "RST",+ "type": "output",+ "description": "The RST open-collector output is driven low when the output voltage is out of regulation and is released after the adjustable DELAY time once the output is over the active delay threshold."+ },+ {+ "number": "2",+ "name": "VCC",+ "type": "power_out",+ "description": "Connect a ceramic capacitor (≥ 470 nF) to filter the internal voltage reference; this pin supplies the embedded analog circuitry, with absolute maximum VCC of -0.3 V to (VIN + 0.3 V) or 4 V max."+ },+ {+ "number": "3",+ "name": "SS/INH",+ "type": "bidirectional",+ "description": "An open-collector stage can disable the device by clamping this pin to GND (INH mode), and an internal 4 µA typ. current generator charges the external capacitor to set the soft-start; absolute maximum is -0.3 V to VIN + 0.3 V."+ },+ {+ "number": "4",+ "name": "SYNCH/ISKIP",+ "type": "input",+ "description": "In LNM this pin provides master/slave synchronization, and in LCM it selects the skip current level; leave it floating when not used in LNM."+ },+ {+ "number": "5",+ "name": "FSW",+ "type": "input",+ "description": "A pull-up resistor (E24 series) to VCC or pull-down to GND selects the switching frequency, with the strapping active only before the soft-start phase."+ },+ {+ "number": "6",+ "name": "MLF",+ "type": "input",+ "description": "A pull-up resistor (E24 series) to VCC or pull-down to GND selects low consumption mode or low noise mode and the active RST threshold, with the strapping active only before the soft-start phase."+ },+ {+ "number": "7",+ "name": "COMP",+ "type": "passive",+ "description": "Output of the error amplifier, to which the designed compensation network is connected."+ },+ {+ "number": "8",+ "name": "DELAY",+ "type": "passive",+ "description": "An external capacitor on this pin sets the delay before RST is released after the output passes the reset threshold; if left floating, RST behaves like a Power Good signal."+ },+ {+ "number": "9",+ "name": "VOUT",+ "type": "input",+ "description": "Output voltage sensing input; absolute maximum rating is -0.3 V to 10 V."+ },+ {+ "number": "10",+ "name": "SGND",+ "type": "power_in",+ "description": "Signal ground; must be connected to the exposed pad together with PGND."+ },+ {+ "number": "11",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground; must be connected to SGND and the exposed pad."+ },+ {+ "number": "12",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground; must be connected to SGND and the exposed pad."+ },+ {+ "number": "13",+ "name": "LX",+ "type": "output",+ "description": "Switching node; absolute maximum rating is -0.3 V to VIN + 0.3 V, and the high-side and low-side switch current is limited to 2 A."+ },+ {+ "number": "14",+ "name": "LX",+ "type": "output",+ "description": "Switching node; absolute maximum rating is -0.3 V to VIN + 0.3 V, and the high-side and low-side switch current is limited to 2 A."+ },+ {+ "number": "15",+ "name": "VIN",+ "type": "power_in",+ "description": "DC input voltage; operating range is 4 V to 38 V with an absolute maximum of 40 V."+ },+ {+ "number": "16",+ "name": "VBIAS",+ "type": "power_in",+ "description": "Typically connected to the regulated output voltage; an external voltage reference can supply part of the analog circuitry to improve light-load efficiency, and it should be connected to GND if not used (absolute maximum -0.3 V to (VIN + 0.3 V) or 6 V max)."+ },+ {+ "number": "17",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The exposed pad is not given a number in the pin table (shown as '-'); it is labelled 'EP' in the ap; Pin 9 is labelled VOUT in the pin table and Figure 2, but labelled FB in the application schematic (; The datasheet does not give ERC types. The types for SS/INH (bidirectional), SYNCH/ISKP, FSW, MLF, V",+ "exposed pad 17 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 15,+ "cost_usd": 0.0677,+ "at": "2026-10-08T15:28:53"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589829662811074560",+ "pages": 68,+ "sha256": "b526b22bab1d8834",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "l6986htr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7982746831c0bd23f4690608869ad67776faae5c762fb0376666126a3998921b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "l6986htr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "dec7fc1962d0d39fce145e688480f5b123fec213d20f34381d2d1823dbb6a30a",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}