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L6986F

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STMicroelectronics DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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L6986F

STMicroelectronics · DC-DC Converters · HTSSOP-16-EP

L6986F from STMicroelectronics, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RST output RST open-collector output is driven low when the output voltage is out of regulation and is released after an adjustable DELAY time once the output is above the active delay threshold.
2 VCC power_out Ceramic capacitor (≥ 470 nF) must be connected to filter the internal voltage reference, and this LDO pin supplies the embedded analog circuitry (VCC LDO output 2.9 V to 3.6 V, 3.3 V typ.).
3 SS/INH bidirectional An open-collector stage can disable the device when this pin is clamped to GND (INH mode), and an internal current generator (4 µA typ.) charges the external capacitor to implement soft-start.
4 SYNCH/ISKP input This pin provides master/slave synchronization in low noise mode (LNM) and selects the skip current level in low consumption mode (LCM).
5 FSW input A pull-up resistor (E24 series) to VCC or pull-down to GND selects the switching frequency, and pinstrapping is active only before the soft-start phase.
6 MLF input A pull-up resistor (E24 series) to VCC or pull-down to GND selects low noise mode or low consumption mode and the active RST threshold, and pinstrapping is active only before the soft-start phase.
7 COMP passive Output of the error amplifier, to which the compensation network is connected (absolute max -0.3 V to VCC + 0.3 V).
8 DELAY passive An external capacitor on this pin sets the time DELAY before the RST output is released after the output exceeds the reset threshold; if left floating, RST behaves like a Power Good signal.
9 FB input Inverting input of the error amplifier, with a voltage feedback reference of 0.841 V to 0.859 V (0.85 V typ.).
10 SGND power_in Signal ground, which must be connected to the exposed pad.
11 PGND power_in Power ground, which must be connected to the exposed pad.
12 PGND power_in Power ground, which must be connected to the exposed pad.
13 LX output Switching node; absolute maximum range is -0.3 V to VIN + 0.3 V and high-side/low-side switch current is limited to 2 A.
14 LX output Switching node; absolute maximum range is -0.3 V to VIN + 0.3 V and high-side/low-side switch current is limited to 2 A.
15 VIN power_in DC input voltage, operating range 4 V to 38 V (absolute maximum 40 V).
16 VBIAS power_in Typically connected to the regulated output voltage; an external voltage reference can supply part of the analog circuitry to improve light-load efficiency, and it must be connected to GND if not used.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package HTSSOP-16-EP
Category Power Management (PMIC)
Pins 17

CAD (KiCad official)

  • Symbol: L6986F
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: l6986f-etched.step / l6986f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6986f.step / l6986f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (64 pp, sha256 2773d92112882ade, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF