L6984ATR from STMicroelectronics, in a DFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	PGOOD	output	Open collector output driven low when the FB voltage is below the VPGD L threshold, with PGOOD low impedance when FB falls to 88 % of VREF (typical).
2	FB	input	Inverting input of the error amplifier, with an absolute maximum range of -0.3 V to VCC + 0.3 V.
3	TON	input	A resistor connected between this pin and VIN sets the switching frequency, adjustable from 250 kHz to 600 kHz.
4	EN	input	Enable pin where a logic active high signal enables the device; connect to VIN if not used, with thresholds of 1.1 V (inhibited) and 2.6 V (enabled).
5	GND	power_in	Power ground of the regulator.
6	LX	output	Switching node, with an absolute maximum range of -0.3 V to VIN + 0.3 V.
7	VIN	power_in	DC input voltage, operating from 4.5 V to 36 V with an absolute maximum of 40 V.
8	VCC	power_out	Embedded regulator output supplying the main switching controller, requiring an external 1 µF capacitor and regulating 3.3 V when VBIAS is below 2.4 V.
9	VBIAS	power_in	Typically connected to the regulated output voltage; an external voltage reference can supply the analog circuitry to increase light load efficiency, and it must be connected to GND if not used.
10	LNM	input	Connect to VCC for low noise mode (LNM) operation or to GND for low consumption mode (LCM) operation.
11	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	DFN-10-EP(3x3)
Category	Power Management ICs
Pins	11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating input voltage range	VIN	4.5		36	V	TJ = 25 °C, VIN = VEN = 12 V, VBIAS = 3.3 V	7
UVLO rising edge	VIN_UVLO	3.1	3.8	4.5	V	rising edge VCC regulator, VBIAS = GND	7
UVLO falling edge	VIN_UVLO	2.9	3.6	4.3	V	falling edge VCC regulator, VBIAS = GND	7
Fixed output voltage valley regulation	VOUT	3.23	3.3	3.37	V	FB = VCC, no load	7
Adjustable output voltage valley regulation	VFB	0.88	0.9	0.92	V	No load, VBIAS = 3.3 V	7
High-side RDSON	RDSON HS	0.9	1.3	1.7	Ω	ISW = 0.1 A	7
Low-side RDSON	RDSON LS	0.6	1	1.4	Ω	ISW = 0.1 A	7
Minimum Low-side conduction time	TOFF	100	300	400	ns	VIN = VEN = 4.5 V	7
Valley current limit	IVY	350	400	470	mA		7
Zero crossing current threshold	IZCD	12	27	46	mA		7
VCC voltage	VCC	3	3.8	4.6	V	VFB = 1 V, VBIAS = GND	7
VBIAS falling threshold	VBIAS	2.4	2.6	2.8	V		7
VBIAS rising threshold	VBIAS	2.6	2.9	3.2	V		7
Shutdown current from VIN	ISHTDWN	3	13	22	µA	EN = GND	7
Quiescent current from VIN, LCM - SWO	IQ OPVIN	11	26	41	µA	VREF < VFB < VOVP (SLEEP), VBIAS = 3.3 V	8
Quiescent current from VIN, LCM - NO SWO	IQ OPVIN	90	160	230	µA	VREF < VFB < VOVP (SLEEP), VBIAS = GND	8
Quiescent current from VIN, LNM - SWO	IQ OPVIN	11	26	42	µA	VREF < VFB < VOVP, VBIAS = 3.3 V	8
Quiescent current from VIN, LNM - NO SWO	IQ OPVIN	200	320	440	µA	VREF < VFB < VOVP, VBIAS = GND	8
Quiescent current from VBIAS, LCM - SWO	IQ OPVBIAS	80	150	200	µA	VREF < VFB < VOVP (SLEEP), VBIAS = 3.3 V	8
Quiescent current from VBIAS, LNM - SWO	IQ OPVBIAS	180	300	390	µA	VREF < VFB < VOVP, VBIAS = 3.3 V	8
Overvoltage trip (VOVP/VREF)	VOVP	18	23	28	%	Rising edge	8
Power Good LOW threshold, VFB falling edge	VPGD L	84	88	92	%	VFB falling edge (PGOOD low impedance)	8
Power Good HIGH threshold, internal FB rising edge	VPGD H	118	123	128	%	Internal FB rising edge (PGOOD low impedance), VFB = VCC	8
PGOOD output low, 4 mA sink	VPGOOD			0.6	V	VIN > VIN_UVLO_H, VFB=GND, 4 mA sinking load	8
PGOOD output low, 100 µA sink	VPGOOD			0.6	V	2.9 < VIN < VIN_UVLO_H, 100 µA sinking load	8
EN threshold, device inhibited	EN			1.1	V	Device inhibited	8
EN threshold, device enabled	EN	2.6			V	Device enabled	8
EN hysteresis			650		mV	Not tested in production	8
Power Good LOW threshold, VFB rising edge	VPGD L			90	%	VFB rising edge (PGOOD high impedance)	8
Power Good HIGH threshold, internal FB falling edge	VPGD H		100		%	Internal FB falling edge (PGOOD high impedance), VFB = VCC	8
Thermal shutdown temperature	TSHDWN		150		°C	Not tested in production	9
Thermal shutdown hysteresis	THYS		20		°C	Not tested in production	9
Input slew rate	dVIN/dt			0.1	V/µs		5
VIN, EN, TON, VBIAS, PGOOD, LNM voltage	VIN	-0.3		40	V	VIN pin (group with EN, TON, VBIAS, PGOOD, LNM per table layout)	5
LX voltage	LX	-0.3			V	max VIN + 0.3	5
VCC voltage	VCC	-0.3		6	V		5
FB voltage	FB	-0.3			V	max VCC + 0.3	5
Operating temperature range	TJ	-40		150	°C		5
Storage temperature range	TSTG	-55		150	°C		5
Lead temperature	TLEAD			260	°C	soldering 10 sec.	5
High-side RMS switch current	IHS			420	mA		5
Low-side RMS switch current	ILS			500	mA		5
Thermal resistance junction ambient	RthJA		50		°C/W	device soldered on the STMicroelectronics evaluation board	5
ESD HBM	ESD			2	kV	HBM	6
ESD MM	ESD			200	V	MM	6
ESD CDM	ESD			500	V	CDM	6

CAD (KiCad official)

Symbol: L6984ATR
Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
3D model: DFN-10-EP(3x3) (KiCad packages3D, STEP)
3D model files: l6984atr-etched.step / l6984atr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6984atr.step / l6984atr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (47 pp, sha256 9a7f76997b209e2b, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

L6984ATR

Verified L6984ATR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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