component
L6982C50DR
Public Made by Adomby adom
STMicroelectronics DC-DC Converters, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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L6982C50DR
STMicroelectronics · DC-DC Converters · SO-8
L6982C50DR from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switching node of the regulator; the datasheet gives no further limits for this pin. |
| 2 | BOOT | passive | Connect an external 100 nF (typ.) capacitor between BOOT and SW; the gate charge for the internal NMOS is refreshed during the low-side switch conduction time. |
| 3 | VCC | power_out | Supplies the embedded analog circuitry and needs a ceramic capacitor of at least 1 µF to filter the internal voltage reference. |
| 4 | FB/VOUT | input | FB is the output voltage sensing input, used with an external voltage divider. |
| 5 | EN/CLKIN | input | Enable pin with an internal voltage divider: pull down to disable and pull up to enable the device; in LNM versions it also accepts an external clock to synchronize the device. |
| 6 | AGND | power_in | Analog ground; the datasheet gives no further limits for this pin. |
| 7 | VIN | power_in | DC input voltage; the features list gives an operating input range of 3.5 V to 38 V. |
| 8 | PGND | power_in | Power ground; the datasheet gives no further limits for this pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
L6982C50DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
l6982c50dr-etched.step/l6982c50dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);l6982c50dr.step/l6982c50dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (50 pp, sha256
71dac5297754a94d, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# L6982C50DR
**STMicroelectronics** · DC-DC Converters · SO-8
L6982C50DR from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switching node of the regulator; the datasheet gives no further limits for this pin. |
| 2 | BOOT | passive | Connect an external 100 nF (typ.) capacitor between BOOT and SW; the gate charge for the internal NMOS is refreshed during the low-side switch conduction time. |
| 3 | VCC | power_out | Supplies the embedded analog circuitry and needs a ceramic capacitor of at least 1 µF to filter the internal voltage reference. |
| 4 | FB/VOUT | input | FB is the output voltage sensing input, used with an external voltage divider. |
| 5 | EN/CLKIN | input | Enable pin with an internal voltage divider: pull down to disable and pull up to enable the device; in LNM versions it also accepts an external clock to synchronize the device. |
| 6 | AGND | power_in | Analog ground; the datasheet gives no further limits for this pin. |
| 7 | VIN | power_in | DC input voltage; the features list gives an operating input range of 3.5 V to 38 V. |
| 8 | PGND | power_in | Power ground; the datasheet gives no further limits for this pin. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## CAD (KiCad official)
- Symbol: `L6982C50DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files: `l6982c50dr-etched.step` / `l6982c50dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l6982c50dr.step` / `l6982c50dr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603173925904142336) (50 pp, sha256 `71dac5297754a94d`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/l6982c50dr-datasheet.pdf)