component

L6981C50DR

Public Made by Adom

by adom

STMicroelectronics DC-DC Converters, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)l6981c50drfactory-2.0.0extractor-text

Verified L6981C50DR

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: L6981C50DR · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 52-page datasheet
  • ✓distributor: lcsc C5268093, digikey 497-L6981C50DRTR-ND, mouser 511-L6981C50DR
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-yxymnw12/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ l6981c50dr.kicad_sym✓ l6981c50dr.kicad_mod✓ l6981c50dr.step
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3D Model

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Symbol & Footprint

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Contents

README

markdown

L6981C50DR

STMicroelectronics · DC-DC Converters · SO-8

L6981C50DR from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SW output Switching node of the synchronous step-down converter.
2 BOOT passive Connect an external 100 nF (typ.) capacitor between BOOT and SW to refresh the gate charge that drives the internal NMOS.
3 VCC power_out Supplies the embedded analog circuitry; connect a ceramic capacitor (≥ 1 µF) to filter the internal voltage reference.
4 VOUT/FB input In fixed output voltage versions such as the 5 V C50 part, VOUT senses the output voltage through an internal voltage divider.
5 EN/CLKIN input Enable pin with internal voltage divider; pull down to disable and pull up to enable the device, and in LNM versions it also accepts an external clock for synchronization.
6 AGND power_in Analog ground.
7 VIN power_in DC input voltage of the regulator.
8 PGND power_in Power ground.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Operating input voltage range VIN 3.5 38 V 6
Enable threshold rising VEN 1.08 1.2 1.32 V Rising 6
VCC LDO output voltage 3 3.3 3.6 V 6
Quiescent current from VIN, fixed VOUT part number (LCM) IQ_VIN 1 3.5 6 μA Fix VOUT part number 6
Quiescent current from VOUT, fixed VOUT part number (LCM) IQ_VOUT 20 35 60 μA Fix VOUT part number 6
Valley current limit IVY 1.7 2 2.3 A 6
Reverse current limit IVY_SINK 1.25 1.5 1.75 A LNM or VOUT overvoltage 6
Switching frequency FSW 360 400 440 KHz 6
Internal soft-start TSS 1 1.3 1.6 ms 6
Voltage feedback, fixed 5.0 V version VFB 4.955 5 5.045 V Fixed 5.0 V version TJ = 25 °C 7
Voltage feedback, fixed 5.0 V version VFB 4.93 5 5.07 V Fixed 5.0 V version TJ = -40 °C ≤ TJ ≤ 125 °C 7
Overvoltage trip (VOVP/VREF) VOVP 115 120 125 % 7
Overvoltage hysteresis VOVP_HYST 1 2 6 % 7
Thermal shutdown temperature TSHDWN 165 °C Not tested in production 7
Thermal shutdown hysteresis THYS 30 °C Not tested in production 7
Maximum pin voltage VIN VIN -0.3 42 V 5
PGND to AGND maximum pin voltage -0.3 0.3 V 5
VOUT/FB maximum pin voltage VOUT/FB -0.3 8 V 5
High-side / low-side RMS switch current IHS, ILS 1.5 A 5
Operating temperature range TJ TJ -40 150 °C 5
Storage temperature range TSTG -65 150 °C 5
Lead temperature (soldering 10 sec.) TLEAD 260 °C Soldering 10 sec. 5
Thermal resistance junction ambient RthJA 65 °C/W Device soldered on the STMicroelectronics 2Layer 2-Oz Cu demonstration board 5

CAD (KiCad official)

  • Symbol: L6981C50DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: l6981c50dr-etched.step / l6981c50dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6981c50dr.step / l6981c50dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (52 pp, sha256 ffbb8bf9e87b0957, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF