L6599DTR

{
  "schema_version": 1,
  "type": "component",
  "slug": "l6599dtr",
  "title": "L6599DTR",
  "brief": "STMicroelectronics AC-DC Controllers and Regulators, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "pmic",
    "l6599dtr"
  ],
  "component": {
    "mpn": "L6599DTR",
    "manufacturer": "STMicroelectronics",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "PMIC",
    "subcategory": "AC-DC Controllers and Regulators",
    "datasheet": "https://www.st.com/resource/en/datasheet/l6599dtr.pdf",
    "parts": {
      "symbol": "l6599dtr.kicad_sym",
      "footprint": "l6599dtr.kicad_mod",
      "model_3d": "l6599dtr-etched.glb",
      "model_3d_plain": "l6599dtr.glb",
      "model_3d_step": "l6599dtr-etched.step",
      "model_3d_step_plain": "l6599dtr.step",
      "lbr": "l6599dtr.lbr"
    },
    "distributor_links": {
      "lcsc": "C28558"
    },
    "pins": [
      {
        "number": "1",
        "name": "CSS",
        "type": "passive",
        "description": "Soft-start pin. External capacitor to GND and resistor to RFmin (pin 4) set the maximum oscillator frequency and the frequency-shift time constant during start-up. Internally discharged whenever the chip turns OFF (VCC<UVLO, LINE<1.25V or >6V, DIS>1.85V, ISEN>1.5V, DELAY>3.5V) and while ISEN exceeds 0.8V (down to 0.75V) so the part always soft-starts."
      },
      {
        "number": "2",
        "name": "DELAY",
        "type": "passive",
        "description": "Delayed shutdown upon overcurrent. External RC to GND sets the maximum duration of an OCP condition (charged by an internal 150 uA current source when ISEN>0.8V) and the restart delay. IC stops switching once the pin reaches 3.5V and re-enables when the voltage falls below 0.3V, yielding hiccup-mode short-circuit protection."
      },
      {
        "number": "3",
        "name": "CF",
        "type": "passive",
        "description": "Timing capacitor. Charged/discharged by internal current sources programmed by the RFmin network to set the converter switching frequency."
      },
      {
        "number": "4",
        "name": "RFmin",
        "type": "passive",
        "description": "Minimum oscillator frequency setting. Provides a precise 2 V reference; the resistor to GND sets the minimum oscillator frequency. The optocoupler phototransistor is coupled here through a resistor to modulate the operating frequency (feedback), and an RC series to GND sets the soft-start frequency shift."
      },
      {
        "number": "5",
        "name": "STBY",
        "type": "input",
        "description": "Burst-mode operation threshold. Compared to an internal 1.25 V reference with 50 mV hysteresis; when the feedback-related voltage falls below the reference, the IC enters idle (burst) mode and drops to reduced quiescent current. Tie to RFmin if burst-mode is not used."
      },
      {
        "number": "6",
        "name": "ISEN",
        "type": "input",
        "description": "Current-sense input for two-level OCP. Above the 0.8 V threshold (50 mV hysteresis) the soft-start cap is discharged, shifting the switching frequency up to limit power. A second 1.5 V comparator latches the device off (near-zero consumption) if the current keeps rising; latch clears when VCC drops below UVLO. Tie to GND if unused."
      },
      {
        "number": "7",
        "name": "LINE",
        "type": "input",
        "description": "Line-sensing input for AC/DC brownout protection. Below 1.25 V the IC shuts down (not latched), consumption drops and the soft-start cap discharges; operation re-enables above 1.25 V. Internal 15 uA current source provides hysteresis while pin is below 1.25 V. An internal zener top-limits the pin; triggering it latches the IC OFF. Bias between 1.25 V and 6 V if unused; bypass to GND for noise immunity."
      },
      {
        "number": "8",
        "name": "DIS",
        "type": "input",
        "description": "Latched device shutdown. When the pin exceeds 1.85 V the IC is latched OFF at near-zero consumption; latch cleared only by recycling VCC below UVLO. Enables easy OTP/OVP implementation. Tie to GND if unused."
      },
      {
        "number": "9",
        "name": "PFC_STOP",
        "type": "output",
        "description": "Open-drain ON/OFF control for the upstream PFC controller. Pulled low when the IC is shut down (DIS>1.85V, ISEN>1.5V, LINE>6V, STBY<1.25V or DELAY>2V) and re-opens after DELAY falls below 0.3V. Open during UVLO. Leave unconnected if unused."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Chip signal/low-side driver ground. All bias-component grounds should return here on a dedicated track kept separate from any pulsed current return."
      },
      {
        "number": "11",
        "name": "LVG",
        "type": "output",
        "description": "Low-side gate-drive output for the half-bridge lower MOSFET. Capable of 0.3 A min source / 0.8 A min sink peak current; actively pulled to GND during UVLO."
      },
      {
        "number": "12",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage for the signal section and the low-side gate driver. Operating range 8.85-16 V, turn-ON ~10.7 V, turn-OFF ~8.15 V, VCC clamp ~17 V. A small (0.1 uF typ.) bypass to GND may be useful to keep clean bias for the signal section."
      },
      {
        "number": "13",
        "name": "N.C.",
        "type": "unconnected",
        "description": "High-voltage spacer. Not internally connected; isolates the high-voltage pins and eases PCB creepage/safety compliance."
      },
      {
        "number": "14",
        "name": "OUT",
        "type": "power_in",
        "description": "High-side gate-drive floating ground and current return for the high-side driver. Rated -3 V to VBOOT-18 V; connects to the half-bridge switching node. Route carefully to avoid large negative spikes."
      },
      {
        "number": "15",
        "name": "HVG",
        "type": "output",
        "description": "High-side floating gate-drive output for the half-bridge upper MOSFET. Capable of 0.3 A min source / 0.8 A min sink peak current. An internal resistor to OUT (pin 14) keeps the pin from floating during UVLO."
      },
      {
        "number": "16",
        "name": "VBOOT",
        "type": "power_in",
        "description": "High-side gate-drive floating supply. Bootstrap capacitor between VBOOT and OUT (pin 14) is refreshed by an internal synchronous bootstrap DMOS driven in phase with the low-side driver, replacing the external fast-recovery diode. Floating supply rated up to 618 V (max), tested to 580 V leakage."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.st.com/resource/en/datasheet/l6599dtr.pdf",
        "pages": 36,
        "sha256": "d3eec3163e3e5244",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -4.445
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
      "mark": "drawn"
    },
    "models_3d": [
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        "file": "l6599dtr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          9.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "l6599dtr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
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        "sha256": "0817b058905e8e4fcce409eed72be18ec16d71b9938a282bd50f1476e09fc4d6",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "STMicroelectronics",
      "Package": "SOIC-16",
      "Category": "PMIC",
      "Pins": "16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "l6599dtr"
  ],
  "discovery_pitch": "L6599DTR (STMicroelectronics) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "l6599dtr.kicad_sym",
    "l6599dtr.kicad_mod",
    "l6599dtr.glb",
    "l6599dtr.step",
    "l6599dtr-etched.step",
    "l6599dtr.lbr",
    "docs/hero.png",
    "docs/l6599dtr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "L6599DTR",
      "kind": "packaging"
    },
    {
      "mpn": "L6599N",
      "kind": "unknown"
    }
  ],
  "updated_at": "2026-09-24T23:29:52.876Z"
}