L6563S

STMicroelectronics · AC-DC Controllers And Regulators · SOIC-14

L6563S from STMicroelectronics, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	INV	input	Inverting input of the error amplifier, fed from the output voltage divider, normally high impedance and sinking a current from TBO only when tracking boost is used.
2	COMP	output	Error amplifier output with a compensation network to INV, and the gate driver is inhibited (burst-mode operation) when the voltage falls below 2.4 V.
3	MULT	input	Mains input to the multiplier, connected to the rectified mains through a resistor divider, providing the sinusoidal current-loop reference and the RMS mains information.
4	CS	input	Input to the PWM comparator for MOSFET current sensing, where a second level at 1.7 V detects abnormal currents and temporarily stops the converter.
5	VFF	input	Second multiplier input for the 1/V² function, requiring a capacitor and parallel resistor to GND, and it must never be connected directly to GND but through a resistor between 100 kΩ (min) and 2 MΩ (max).
6	TBO	passive	Tracking boost pin providing a buffered VFF voltage, where a resistor to GND sets the current sunk from INV, and it must be left open if the function is not used.
7	PFC_OK	input	PFC output voltage monitor and remote disable, where the IC stops switching above 2.5 V, shuts down below 0.23 V (restarts above 0.27 V), and latches off on feedback failure when INV is below 1.66 V.
8	PWM_LATCH	output	Fault output asserted high on feedback failure to latch off the cascaded dc-dc PWM controller, high impedance in normal operation and left floating if not used.
9	PWM_STOP	output	Fault output pulled to ground when RUN is below 0.8 V to temporarily stop the dc-dc PWM controller, high impedance in normal operation with a maximum sink current of 3 mA.
10	RUN	input	Remote ON/OFF control where a voltage below 0.8 V shuts down the IC without latching and restart occurs above 0.88 V, and it can be connected to VFF for brownout protection.
11	ZCD	input	Boost inductor demagnetization sensing input for transition-mode operation, where a negative-going edge triggers MOSFET turn-on, with a maximum current of -10 mA (source) and 10 mA (sink).
12	GND	power_in	Ground, serving as the current return for both the signal part of the IC and the gate driver.
13	GD	output	Totem-pole gate driver output for power MOSFETs and IGBTs with 600 mA peak source and 800 mA peak sink current, with the high level clamped at about 12 V.
14	Vcc	power_in	Supply voltage for both the signal part of the IC and the gate driver, self-limited at 20 mA, with a bypass capacitor of about 0.1 µF typical to GND suggested for a clean bias.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SOIC-14
Category	Power Management (PMIC)
Pins	14

CAD (KiCad official)

Symbol: L6563S
Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
3D model: SOIC-14 (KiCad packages3D, STEP)
3D model files: l6563s-etched.step / l6563s-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6563s.step / l6563s.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (43 pp, sha256 49f8e8c4ab183a43, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# L6563S

**STMicroelectronics** · AC-DC Controllers And Regulators · SOIC-14

L6563S from STMicroelectronics, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INV | input | Inverting input of the error amplifier, fed from the output voltage divider, normally high impedance and sinking a current from TBO only when tracking boost is used. |
| 2 | COMP | output | Error amplifier output with a compensation network to INV, and the gate driver is inhibited (burst-mode operation) when the voltage falls below 2.4 V. |
| 3 | MULT | input | Mains input to the multiplier, connected to the rectified mains through a resistor divider, providing the sinusoidal current-loop reference and the RMS mains information. |
| 4 | CS | input | Input to the PWM comparator for MOSFET current sensing, where a second level at 1.7 V detects abnormal currents and temporarily stops the converter. |
| 5 | VFF | input | Second multiplier input for the 1/V² function, requiring a capacitor and parallel resistor to GND, and it must never be connected directly to GND but through a resistor between 100 kΩ (min) and 2 MΩ (max). |
| 6 | TBO | passive | Tracking boost pin providing a buffered VFF voltage, where a resistor to GND sets the current sunk from INV, and it must be left open if the function is not used. |
| 7 | PFC_OK | input | PFC output voltage monitor and remote disable, where the IC stops switching above 2.5 V, shuts down below 0.23 V (restarts above 0.27 V), and latches off on feedback failure when INV is below 1.66 V. |
| 8 | PWM_LATCH | output | Fault output asserted high on feedback failure to latch off the cascaded dc-dc PWM controller, high impedance in normal operation and left floating if not used. |
| 9 | PWM_STOP | output | Fault output pulled to ground when RUN is below 0.8 V to temporarily stop the dc-dc PWM controller, high impedance in normal operation with a maximum sink current of 3 mA. |
| 10 | RUN | input | Remote ON/OFF control where a voltage below 0.8 V shuts down the IC without latching and restart occurs above 0.88 V, and it can be connected to VFF for brownout protection. |
| 11 | ZCD | input | Boost inductor demagnetization sensing input for transition-mode operation, where a negative-going edge triggers MOSFET turn-on, with a maximum current of -10 mA (source) and 10 mA (sink). |
| 12 | GND | power_in | Ground, serving as the current return for both the signal part of the IC and the gate driver. |
| 13 | GD | output | Totem-pole gate driver output for power MOSFETs and IGBTs with 600 mA peak source and 800 mA peak sink current, with the high level clamped at about 12 V. |
| 14 | Vcc | power_in | Supply voltage for both the signal part of the IC and the gate driver, self-limited at 20 mA, with a bypass capacitor of about 0.1 µF typical to GND suggested for a clean bias. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `L6563S`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `l6563s-etched.step` / `l6563s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l6563s.step` / `l6563s.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8603086101364568064) (43 pp, sha256 `49f8e8c4ab183a43`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l6563s-datasheet.pdf)