L6563HTR from STMicroelectronics, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	INV	input	Inverting input of the error amplifier that receives the PFC output voltage information through a resistor divider; it normally has high impedance and sinks current when tracking boost is used.
2	COMP	output	Output of the error amplifier with a compensation network to INV; the gate driver is inhibited when the voltage falls below 2.4 V (burst-mode operation).
3	MULT	input	Mains input to the multiplier, connected to the rectified mains via a resistor divider, with a linear operation range of 0 to 3 V.
4	CS	input	Input to the PWM comparator sensing MOSFET current, with a second comparison level at 1.7 V detecting abnormal currents such as boost inductor saturation.
5	VFF	input	Second multiplier input for the 1/V² function; a capacitor and parallel resistor to GND are required, and the pin must never be connected directly to GND but through a resistor from 100 kΩ (min) to 2 MΩ (max).
6	TBO	passive	Tracking boost function pin providing a buffered VFF voltage; a resistor to GND sets the current sunk from INV, and it is left open if the function is not used.
7	PFC_OK	input	PFC output voltage monitoring and disable pin: above 2.5 V the IC stops switching, below 0.23 V the IC is shut down, and it restarts above 0.27 V.
8	PWM_LATCH	output	Fault signaling output that is asserted high on feedback failure (PFC_OK > 2.5 V and INV < 1.66 V) to latch off the downstream PWM controller, and left floating if not used.
9	HVS	power_in	High voltage start-up pin, able to withstand 700 V, tied directly to the rectified mains voltage; the absolute voltage range referred to ground is -0.3 to 700 V.
10	N.C.	unconnected	Not internally connected; provides clearance on the PCB to meet safety requirements.
11	PWM_STOP	output	Fault signaling output that is pulled to ground when the IC is disabled by a voltage below 0.8 V on RUN, with a maximum sink current of 3 mA, and left floating if not used.
12	RUN	input	Remote ON/OFF control where a voltage below 0.8 V shuts down the IC (not latched) and it restarts above 0.88 V; it can be connected to VFF for brownout protection.
13	ZCD	input	Boost inductor demagnetization sensing input for transition-mode operation, where a negative-going edge triggers MOSFET turn-on; the zero current detector maximum current is -10 mA (source) and 10 mA (sink).
14	GND	power_in	Ground, serving as the current return for both the signal part of the IC and the gate driver.
15	GD	output	Totem pole gate driver output able to drive power MOSFETs and IGBTs with 600 mA peak source and 800 mA peak sink, with the high level clamped at about 12 V.
16	Vcc	power_in	Supply voltage for both the signal part of the IC and the gate driver, with an operating range of 10.3 V to 22.5 V after turn-on.

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	SO-16
Category	Power Management (PMIC)
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating range	Vcc	10.3		22.5	V	After turn-on	11
Turn-on threshold	VccOn	11	12	13	V		11
Turn-off threshold	VccOff	8.7	9.5	10.3	V		11
Vcc for resuming from latch	Vccrestart	5	6	7	V	OVP latched	11
Hysteresis	Hys	2.3		2.7	V		11
Zener voltage	VZ	22.5	25	28	V	Icc = 20 mA	11
Start-up current	Istart-up		90	150	µA	Before turn-on, Vcc = 10 V	11
Quiescent current	Iq		4	5	mA	After turn-on, VMULT = 1 V	11
Operating supply current	ICC		5	6	mA	At 70 kHz	11
Idle state quiescent current	Iqdis		180	280	µA	VPFC_OK > VPFC_OK_S AND VINV < VPFC_OK, VFFD	11
Idle state quiescent current	Iqdis		1.5	2.2	mA	VPFC_OK < VPFC_OK_D OR VRUN < VDIS	11
Quiescent current	Iq		2.2	3	mA	VPFC_OK > VPFC_OK_S OR VCOMP < 2.3 V	11
Breakdown voltage	VHV	700			V	IHV < 100 µA	11
Start voltage	VHVstart	65	80	100	V	IVcc < 100 µA	11
Vcc charge current	Icharge	0.55	0.85	1	mA	VHV > VHvstart, Vcc > 3 V	11
ON-state current	IHV, ON			1.6	mA	VHV > VHvstart, Vcc > 3 V	11
ON-state current	IHV, ON			0.8	mA	VHV > VHvstart, Vcc = 0	11
OFF-state leakage current	IHV, OFF			40	µA	VHV = 400 V	11
Vcc restart voltage	VCCrestart	5	6	7	V	Vcc falling	11
Vcc restart voltage	VCCrestart	8.7	9.5	10.3	V	IC latched off (1)	11
Input bias current	IMULT		-0.2	-1	µA	VMULT = 0 to 3 V	11
Linear operation range	VMULT	0		3	V		11
Internal clamp level	VCLAMP	9	9.5		V	IMULT = 1 mA	11
Output max slope	∆Vcs/∆VMULT	2.2	2.34		V/V	VMULT = 0 to 0.4 V, VVFF = 0.8 V, VCOMP = Upper clamp	12
Gain	KM	0.375	0.45	0.525	1/V	VMULT = 1 V, VCOMP = 4 V	12
Voltage feedback input threshold	VINV	2.475	2.5	2.525	V	TJ = 25 °C	12
Voltage feedback input threshold	VINV	2.455		2.545	V	10.3 V < Vcc < 22.5 V	12
Line regulation			2	5	mV	Vcc = 10.3 V to 22.5 V	12
Input bias current	IINV		-0.2	-1	µA	TBO open, VINV = 0 to 4 V	12
Internal clamp level	VINVCLAMP	8	9		V	IINV = 1 mA	12
Voltage gain	Gv	60	80		dB	Open loop	12
Source current	ICOMP	2	4		mA	VCOMP = 4 V, VINV = 2.4 V	12
Sink current	ICOMP	2.5	4.5		mA	VCOMP = 4 V, VINV = 2.6 V	12
Upper clamp voltage	VCOMP	5.7	6.2	6.7	V	ISOURCE = 0.5 mA	12
Burst-mode voltage	VCOMP	2.3	2.4	2.5	V		12
Lower clamp voltage	VCOMP	2.1	2.25	2.4	V	ISINK = 0.5 mA	12
Input bias current	ICS			1	µA	VCS = 0	12
Leading edge blanking	tLEB	100	150	250	ns		12
Delay to output	td(H-L)	100	200	300	ns		12
Current sense reference clamp	VCSclamp	1	1.08	1.16	V	VCOMP = upper clamp, VMULT = 1 V, VVFF = 1 V	12
Current sense offset	Vcsofst		40	70	mV	VMULT = 0, VVFF = 3 V	12
Threshold on current sense	VCS_th	1.6	1.7	1.8	V		12
E/A input pull-up current	IINV	7	10	13	µA	After VCS > VCS_th, before restarting	12
Input bias current	IPFC_OK		-0.1	-1	µA	VPFC_OK = 0 to 2.6 V	12
Clamp voltage	VPFC_OK_C	9	9.5		V	IPFC_OK = 1 mA	12
OVP threshold	VPFC_OK_S	2.435	2.5	2.565	V	voltage rising	12
Restart threshold after OVP	VPFC_OK_R	2.34	2.4	2.46	V	voltage falling	12
Disable threshold	VPFC_OK_D	0.12		0.35	V	voltage falling	12
Disable threshold	VPFC_OK_D	0.17	0.23	0.29	V	TJ = 25 °C	12
Enable threshold	VPFC_OK_E	0.15		0.38	V	voltage rising	13
Feedback failure detection threshold (VINV falling)	VFFD	1.61	1.66	1.71	mV	VPFC_OK = VPFC_OK_S	13
Voltage range (referred to ground)	VHVS	-0.3		700	V	Pin 9	7
Analog inputs and outputs		-0.3		8	V	Pins 2, 4 to 6, 8, 11, 12	7
Max. sink current	IPWM_STOP			3	mA	Pin 11	7
Zero current detector max. current	IZCD	-10		10	mA	-10 (source), 10 (sink); pin 13	7
Max. thermal resistance, junction to ambient	RthJA			120	°C/W	Junction to ambient	7
Junction temperature operating range	TJ	-40		150	°C		7
Storage temperature	Tstg	-55		150	°C		7

CAD (KiCad official)

Symbol: L6563HTR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SO-16 (KiCad packages3D, STEP)
3D model files: l6563htr-etched.step / l6563htr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6563htr.step / l6563htr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (50 pp, sha256 d4f10d4ad8def322, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

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L6563HTR

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