Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

L6563ATR

STMicroelectronics · AC-DC Controllers And Regulators · SOIC-14

L6563ATR from STMicroelectronics, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INV input Inverting input of error amplifier for output voltage feedback via resistor divider; input impedance high, can sink current from TBO pin during tracking boost operation.
2 COMP output Error amplifier output with frequency compensation network to INV pin; output clamp voltage 2.1 to 6.7V depending on input state.
3 MULT input Multiplier main input receiving rectified mains voltage reference via resistor divider; linear operation 0 to 3V with internal clamp at 9 to 9.5V.
4 CS input PWM comparator current sense input detecting MOSFET current through sense resistor; normal operation limit ~1.08V for turn-off comparison.
5 VFF input Voltage feedforward input for 1/V² compensation; connect external RC peak-holding network to ground; operating range 0.5 to 3V with 20mV dropout from MULT peak.
6 TBO output Tracking boost output providing buffered VFF voltage; external resistor to ground defines mains-tracking current sink from INV pin (maximum current 0.25mA).
7 PFC_OK input PFC output voltage monitor input for feedback failure protection; latch-off when exceeds 2.5V or auto-disable when below 0.2V with re-enable threshold 0.26V.
8 PWM_LATCH tri_state Open-source fault output asserted high (3.7V minimum) when PFC_OK exceeds 2.5V for feedback failure detection; signals cascaded DC-DC converter PWM controller with latched shutdown.
9 PWM_STOP tri_state Open-drain fault output pulled low (1V at 0.5mA sink) when RUN input disabled below 0.52V; signals temporary disable to cascaded DC-DC converter PWM controller.
10 RUN input Remote ON/OFF control input for brownout protection; disable threshold 0.5 to 0.54V, re-enable threshold 0.56 to 0.64V with hysteresis for non-latched shutdown.
11 ZCD input Zero-current detector input for boost inductor demagnetization sensing in transition-mode operation; negative-going edge triggers MOSFET turn-on.
12 GND power_in Ground; signal and power current return for IC logic and gate driver output stage.
13 GD output Gate driver output with 600mA source and 800mA sink peak current capability for driving power MOSFETs and IGBTs; output voltage clamped to approximately 12V.
14 VCC power_in Supply voltage for IC logic and gate driver stages; operating range 10.3 to 22V with turn-on at 11 to 13V, turn-off at 8.7 to 10.3V, and Zener clamp at 22 to 25V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-14
Category Power Management (PMIC)
Pins 14

CAD (KiCad official)

  • Symbol: L6563ATR
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: l6563atr-etched.step / l6563atr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6563atr.step / l6563atr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (39 pp, sha256 867a46c1733f77b9, retrieved 2026-09-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF