# L6563A

**STMicroelectronics** · AC-DC Controllers And Regulators · SOIC-14

L6563A from STMicroelectronics, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | INV | input | Inverting input of the error amplifier, fed from the PFC output divider, and it sinks a TBO-programmed current only when tracking boost is used. |
| 2 | COMP | output | Output of the error amplifier, compensated to INV (pin 1) to achieve loop stability and low THD. |
| 3 | MULT | input | Main multiplier input connected to the rectified mains through a resistor divider, providing the sinusoidal current reference and RMS mains information. |
| 4 | CS | input | Input to the PWM comparator that senses MOSFET current through a resistor to determine turn-off; the 1.7V abnormal-current comparison is not present in the L6563A. |
| 5 | VFF | input | Second multiplier input for the 1/V2 function, requiring a capacitor and parallel resistor to GND, and it must never be connected directly to GND. |
| 6 | TBO | passive | Tracking boost pin providing a buffered VFF voltage; a resistor to GND sets the current sunk from INV, and the pin is left open if the function is unused. |
| 7 | PFC_OK | input | PFC output voltage monitor: above 2.5V the IC latches off, and below 0.2V it shuts down until the voltage exceeds 0.26V; tie to 0.26 to 2.5V if unused. |
| 8 | PWM_LATCH | output | Fault output asserted high when PFC_OK exceeds 2.5V, used to latch-disable the DC-DC converter PWM controller; high impedance in normal operation. |
| 9 | PWM_STOP | output | Fault output pulled to ground when RUN is below 0.5V, used to temporarily disable the DC-DC converter PWM controller; high impedance in normal operation. |
| 10 | RUN | input | Remote ON/OFF control: below 0.52V shuts the IC down without latching and it restarts above 0.6V, and it can be tied to VFF for brownout protection. |
| 11 | ZCD | input | Boost inductor demagnetization sensing input for transition-mode operation, where a negative-going edge triggers MOSFET turn-on. |
| 12 | GND | power_in | Ground return for both the signal part of the IC and the gate driver. |
| 13 | GD | output | Totem-pole gate driver output rated 600 mA source and 800 mA sink, with the high-level voltage clamped at about 12V. |
| 14 | VCC | power_in | Supply voltage of both the signal part of the IC and the gate driver. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-14 |
| Category | Power Management (PMIC) |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating range (Vcc) | Vcc | 10.3 |  | 22 | V | After turn-on | 7 |
| Analog inputs & outputs voltage |  | -0.3 |  | 8 | V |  | 6 |
| Max. sink current | IPWM_STOP |  |  | 3 | mA |  | 6 |
| Zero current detector max. current | IZCD | -10 |  | 10 | mA | -10 (source), 10 (sink) | 6 |
| Power dissipation | PTOT |  |  | 0.75 | W | TA = 50°C | 6 |
| Junction temperature operating range | TJ | -25 |  | 150 | °C |  | 6 |
| Storage temperature | TSTG | -55 |  | 150 | °C |  | 6 |
| Maximum thermal resistance junction-ambient | RthJA |  |  | 120 | °C/W |  | 6 |
| Turn-on threshold | VccOn | 11 | 12 | 13 | V |  | 7 |
| Turn-off threshold | VccOff | 8.7 | 9.5 | 10.3 | V |  | 7 |
| Hysteresis | Hys |  | 2.3 | 2.7 | V |  | 7 |
| Zener voltage | VZ | 22 | 25 | 28 | V | Icc = 20 mA | 7 |
| Start-up current | Istart-up |  | 50 | 90 | µA | Before turn-on, Vcc = 10V | 7 |
| Quiescent current | Iq |  | 3 | 5 | mA | After turn-on | 7 |
| Operating supply current | ICC |  | 3.8 | 5.5 | mA | @ 70kHz | 7 |
| Idle state quiescent current (latched) | Iqdis |  | 180 | 250 | µA | Latched by PFC_OK > Vthl or Vcs > VCSdis | 7 |
| Idle state quiescent current (disabled) | Iqdis |  | 1.5 | 2.2 | mA | Disabled by PFC_OK < Vth or RUN < VDIS | 7 |
| Multiplier input bias current | IMULT |  | -0.2 | -1 | µA | VMULT = 0 to 3 V | 7 |
| Multiplier linear operation range | VMULT | 0 |  | 3 | V |  | 7 |
| Multiplier internal clamp level | VCLAMP |  | 9 | 9.5 | V | IMULT = 1 mA | 7 |
| Output max. slope |  |  | 2.2 | 2.34 | V/V | VMULT=0 to 0.5V, VFF=0.8V, VCOMP = Upper clamp | 7 |
| Multiplier gain | KM | 0.375 | 0.45 | 0.525 | V | VMULT = 1 V, VCOMP= 4 V, VVFF = VMULT | 7 |
| Voltage feedback input threshold (TJ = 25 °C) | VINV | 2.465 | 2.5 | 2.535 | V | TJ = 25 °C | 7 |
| Voltage feedback input threshold (over Vcc) | VINV | 2.44 |  | 2.56 | V | 10.3 V < Vcc < 22 V | 7 |
| Line regulation |  |  | 2 | 5 | mV | Vcc = 10.3 V to 22V | 7 |
| Error amplifier input bias current | IINV |  | -0.2 | -1 | µA | TBO open, VINV = 0 to 4 V | 7 |
| Voltage gain | Gv | 60 | 80 |  | dB | Open loop | 8 |
| Gain-bandwidth product | GB |  | 1 |  | MHz |  | 8 |
| Error amplifier source current | ICOMP | -2 | -3.5 | -5 | mA | VCOMP = 4V, VINV = 2.4 V | 8 |
| Error amplifier sink current | ICOMP |  | 2.5 | 4.5 | mA | VCOMP = 4V, VINV = 2.6 V | 8 |
| Upper clamp voltage | VCOMP | 5.7 | 6.2 | 6.7 | V | ISOURCE = 0.5 mA | 8 |
| Lower clamp voltage | VCOMP | 2.1 | 2.25 | 2.4 | V | ISINK = 0.5 mA | 8 |
| Current sense input bias current | ICS |  | -1 |  | µA | VCS = 0 | 8 |
| Leading edge blanking | tLEB | 100 | 200 | 300 | ns |  | 8 |
| Delay to output | td(H-L) |  | 120 |  | ns |  | 8 |
| Current sense reference clamp | VCSclamp | 1 | 1.08 | 1.16 | V | VCOMP = Upper clamp, VVFF = VMULT = 0.5V | 8 |
| Current sense offset | Vcsoffset |  | 25 |  | mV | VMULT = 0, VVFF = 3V | 8 |
| Dynamic OVP triggering current | IOVP | 17 | 20 | 23 | µA |  | 8 |
| Static OVP threshold |  | 2 | 2.15 | 2.3 | V |  | 8 |
| Voltage feedforward linear operation range | VVFF | 0.5 |  | 3 | V | RFF = 47 kΩ to GND | 8 |
| Voltage feedforward dropout | ΔV |  | 20 |  | mV | VMULTpk-VVFF | 8 |
| ZCD upper clamp voltage | VZCDH |  | 5 | 5.7 | V | IZCD = 2.5 mA | 9 |
| ZCD lower clamp voltage | VZCDL | -0.3 | 0 | 0.3 | V | IZCD = -2.5 mA | 9 |
| ZCD triggering voltage (negative-going edge) | VZCDT |  | 0.7 |  | V |  | 9 |
| Tracking boost dropout voltage | ΔV |  | 20 |  | mV | VVFF - VTBO, ITBO = 0.25 mA | 9 |
| Tracking boost linear operation | ITBO | 0 |  | 0.25 | mA |  | 9 |
| IINV - ITBO current mismatch |  | -3.5 |  | 3.5 | % | ITBO = 25 µA to 0.25 mA | 9 |
| Tracking boost clamp voltage | VTBOclamp | 2.9 | 3 | 3.1 | V | VVFF = 4V | 9 |
| PFC_OK latch-off threshold | Vthl | 2.4 | 2.5 | 2.6 | V | Voltage rising | 9 |
| PFC_OK disable threshold | Vth |  | 0.2 |  | V | Voltage falling | 9 |
| PFC_OK enable threshold | VEN |  | 0.26 |  | V | Voltage rising | 9 |
| PFC_OK input bias current | IPFC_OK |  | -0.1 | -1 | µA | VPFC_OK = 0 to 2.5V | 9 |
| PWM_LATCH high level voltage | VH | 3.7 |  |  | V | IPWM_LATCH = -0.5 mA | 9 |
| PWM_LATCH low level leakage current | Ileak | -1 |  |  | µA | VPWM_LATCH=0 | 9 |
| PWM_STOP high level leakage current | Ileak |  | 1 |  | µA | VPWM_STOP = 6V | 9 |
| PWM_STOP low level voltage | VL |  | 1 |  | V | IPWM_STOP = 0.5 mA | 9 |
| Run input bias current | IRUN | -1 |  |  | µA | VRUN = 0 to 3 V | 10 |
| Run disable threshold | VDIS | 0.5 | 0.52 | 0.54 | V | Voltage falling | 10 |
| Run enable threshold | VEN | 0.56 | 0.6 | 0.64 | V | Voltage rising | 10 |
| Start timer period | tSTART | 75 | 150 | 300 | µs |  | 10 |
| Gate driver dropout voltage (source) | VOHdrop |  | 2 | 2.6 | V | IGDsource = 20 mA | 10 |
| Gate driver dropout voltage (source high current) | VOHdrop |  | 2.5 | 3 | V | IGDsource = 200 mA | 10 |
| Gate driver dropout voltage (sink) | VOLdrop |  | 1 | 2 | V | IGDsink = 200 mA | 10 |
| Current fall time | tf |  | 30 | 70 | ns |  | 10 |
| Current rise time | tr |  | 40 | 80 | ns |  | 10 |
| Output clamp voltage | VOclamp | 10 | 12 | 15 | V | IGDsource = 5mA; Vcc = 20V | 10 |
| UVLO saturation |  |  | 1.1 |  | V | Vcc=0 to VccOn, Isink=10mA | 10 |

## CAD (KiCad official)

- Symbol: `L6563A`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `l6563a-etched.step` / `l6563a-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l6563a.step` / `l6563a.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://www.st.com/resource/en/datasheet/l6563a.pdf) (39 pp, sha256 `867a46c1733f77b9`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l6563a-datasheet.pdf)