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Contents

README

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L6562DTR

STMicroelectronics · AC-DC Controllers And Regulators · SO-8

L6562DTR from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INV input Inverting input of the error amplifier; receives output voltage feedback from a resistor divider; analog input with voltage range -0.3 to 8 V and threshold voltage 2.465 to 2.535 V @ 25°C.
2 COMP output Output of the error amplifier with compensation network between this pin and INV for voltage loop stability and high power factor; voltage range -0.3 to 8 V, clamped between 2.1 V (lower) and 5.3 to 6 V (upper).
3 MULT input Main input to the multiplier connected to rectified mains voltage via resistor divider; provides sinusoidal reference to current loop; linear operation range 0 to 3 V with voltage range -0.3 to 8 V.
4 CS input Input to the PWM comparator for MOSFET current sensing via resistor; compared against internal sinusoidal reference to determine MOSFET turn-off; voltage range -0.3 to 8 V, clamped at 1.6 to 1.8 V.
5 ZCD input Boost inductor demagnetization sensing input for transition-mode operation; negative-going edge triggers MOSFET turn-on; maximum current -50 mA (source) and 10 mA (sink); upper clamp 5.0 to 6.5 V, lower clamp 0.3 to 1 V.
6 GND power_in Ground; current return path for both the signal part and gate driver circuits.
7 GD output Gate driver output with totem pole configuration; capable of 600 mA source and 800 mA sink current for MOSFET and IGBT drive; output clamped at approximately 12 V to limit gate voltage stress.
8 Vcc power_in Supply voltage for both signal circuits and gate driver; operating range 10.3 to 22 V; zener clamped at 22 to 28 V; self-limited above 25 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SO-8
Category Power Management (PMIC)
Pins 8

CAD (KiCad official)

  • Symbol: L6562DTR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: l6562dtr-etched.step / l6562dtr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6562dtr.step / l6562dtr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (16 pp, sha256 015ac73cbd46a605, retrieved 2026-09-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF