L6474HTR from STMicroelectronics, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	OUT1A	output	Full bridge A output 1.
2	VSA	power_in	Full bridge A power supply pin; it must be connected to VSB.
3	STBY\RST	input	Standby and reset pin: LOW logic level resets the logic and puts the device into standby mode; if not used, it should be connected to VDD.
4	DIR	input	Direction input.
5	ADCIN	input	Internal analog to digital converter input.
6	VREG	power_out	Internal 3 V voltage regulator output and 3.3 V external logic supply.
7	OSCIN	input	Oscillator pin 1: connects an external oscillator or clock source; if unused, it should be left floating.
8	OSCOUT	output	Oscillator pin 2: connects an external oscillator; when the internal oscillator is used this pin can supply 2/4/8/16 MHz, and if unused it should be left floating.
9	AGND	power_in	Analog ground.
10	CP	output	Charge pump oscillator output.
11	VBOOT	power_in	Bootstrap voltage needed for driving the high-side power DMOS of both bridges (A and B).
12	VSB	power_in	Full bridge B power supply pin; it must be connected to VSA.
13	PGND	power_in	Power ground pin.
14	OUT1B	output	Full bridge B output 1.
15	OUT2B	output	Full bridge B output 2.
16	VSB	power_in	Full bridge B power supply pin; it must be connected to VSA.
17	VDD	power_in	Logic outputs supply voltage (pull-up reference).
18	SDO	output	Data output pin for serial interface.
19	CK	input	Serial interface clock.
20	SDI	input	Data input pin for serial interface.
21	DGND	power_in	Digital ground.
22	SYNC	output	Synchronization signal, open drain output.
23	CS	input	Chip select input pin for serial interface.
24	FLAG	output	Status flag pin: an internal open drain transistor can pull the pin to GND when a programmed alarm condition occurs (step loss, OCD, thermal pre-warning or shutdown, UVLO, wrong command, non performable command).
25	STCK	input	Step clock input.
26	VSA	power_in	Full bridge A power supply pin; it must be connected to VSB.
27	PGND	power_in	Power ground pin.
28	OUT2A	output	Full bridge A output 2.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	STMicroelectronics
Package	HTSSOP-28-EP
Category	Power Management ICs
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Ground differential voltage	VGND,diff	-0.3		0.3	V	Differential voltage between AGND, PGND and DGND	8
ADC input voltage range	VADCIN	-0.3		3.6	V		8
OSCIN and OSCOUT pin voltage range	VOSC	-0.3		3.6	V		8
Logic inputs voltage range	VLOGIC	-0.3		5.5	V		8
Operating junction temperature	TOP	-40		150	°C		8
Storage temperature range	Ts	-55		150	°C		8
Motor supply voltage	VS	8		45	V	VSA = VSB = VS	9
Differential voltage between VSA, OUT1A, OUT2A, PGND and VSB, OUT1B, OUT2B, PGND pins	Vout_diff			45	V	VSA = VSB = VS	9
Logic supply voltage	VREG,in	3.2		3.3	V	VREG voltage imposed by external source	9
VS UVLO turn-on threshold	VSthOn	7.5	8.2	8.9	V		10
VS UVLO turn-off threshold	VSthOff	6.6	7.2	7.8	V		10
VS UVLO threshold hysteresis	VSthHyst	0.7	1	1.3	V		10
Quiescent motor supply current	Iq		0.5	0.65	mA	Internal oscillator selected; VREG = 3.3 V ext; CP floating	10
Minimum charge pump oscillator frequency	fpump,min	660			kHz		10
Maximum charge pump oscillator frequency	fpump,max			800	kHz		10
Low logic level input voltage	VIL			0.8	V		12
High logic level input voltage	VIH	2			V		12
Low logic level output voltage	VOL			0.3	V	VDD = 3.3 V, IOL = 4 mA	12
High logic level output voltage	VOH	2.4			V	VDD = 3.3 V, IOH = 4 mA	12
High logic level output voltage	VOH	4.7			V	VDD = 5 V, IOH = 4 mA	12
CS pull-up and STBY pull-down resistors	RPU	335	430	565	kΩ	CS = GND; STBY/RST = 5 V	12
DIR input pull-up resistance	RPUDIR	60	85	110	kΩ	DIR = GND	12
Internal oscillator frequency tolerance	fosc,i	-3		3	%	Tj = 25 °C, VREG = 3.3 V	12
Programmable external oscillator frequency	fosc,e	8		32	MHz		12
OSCOUT clock source high level voltage	VOSCOUTH	2.4			V	Internal oscillator 3.3 V VREG externally supplied; IOSCOUT = 4 mA	12
OSCOUT clock source low level voltage	VOSCOUTL			0.3	V	Internal oscillator 3.3 V VREG externally supplied; IOSCOUT = 4 mA	12
Step clock input frequency	fSTCK			2	MHz		12
Maximum SPI clock frequency	fCK,MAX			5	MHz		12
Chip select setup time	tsetCS	350			ns		12
Chip select hold time	tholCS	10			ns		12
Deselect time	tdisCS	800			ns		13
Data input setup time	tsetSDI	25			ns		13
Data input hold time	tholSDI	20			ns		13
Data output enable time	tenSDO			38	ns		13
Data output disable time	tdisSDO			47	ns		13
Data output valid time	tvSDO			57	ns		13
Data output hold time	tholSDO	37			ns		13
Max. programmable reference current	ISTEP,max			4	A		13
Min. programmable reference current	ISTEP,min	31			mA		13
Maximum programmable overcurrent detection threshold	IOCD,MAX			6	A	OCD_TH = ‘1111’	13
Minimum programmable overcurrent detection threshold	IOCD,MIN	0.375			A	OCD_TH = ‘0000’	13
Minimum standby time	tSTBY,min	10			µs		13
Voltage regulator output voltage	VREG	2.9	3	3.2	V		13
Voltage regulator output voltage drop	VREG,drop			50	mV	IREG = 40 mA	13
Logic interface supply voltage	VDD			5.5	V		8
Motor supply voltage	VS			48	V	VSA = VSB = VS	8
Bootstrap peak voltage	Vboot			55	V		8
Internal voltage regulator output pin and logic supply voltage	VREG			3.6	V		8
Differential voltage between VSA, OUT1A, OUT2A, PGND and VSB, OUT1B, OUT2B, PGND pins	Vout_diff			48	V	VSA = VSB = VS	8
R.m.s. output current	Iout			3	A		8
Pulsed output current	Iout_peak			7	A	TPULSE < 1 ms	8
Total power dissipation	Ptot			5	W	TA = 25 ºC	8
Logic internal supply current 3.3 V	Ilogic		3.7	4.3	mA	3.3 V VREG externally supplied, internal oscillator	12
Quiescent motor supply current in standby conditions	IqSTBY		26	34	µA	VS = 8 V	13
Quiescent motor supply current in standby conditions	IqSTBY		30	36	µA	VS = 36 V	13
Logic power-on and wake-up time	tlogicwu		38	45	µs		13
Charge pump power-on and wake-up time	tcpwu			650	µs	Power bridges disabled, Cp = 10 nF, Cboot = 220 nF	13
Standby mode internal logic supply current	Ilogic,STBY		2	2.5	µA	3.3 V VREG externally supplied	12
Thermal resistance junction-ambient	RthJA		22		°C/W	HTSSOP28 mounted on EVAL6474H Rev 1.0 board	9

CAD (KiCad official)

Symbol: L6474HTR
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
3D model files: l6474htr-etched.step / l6474htr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l6474htr.step / l6474htr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: STMicroelectronics datasheet (53 pp, sha256 fa9e2a4c268ffbcb, retrieved 2026-11-02, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

L6474HTR

Verified L6474HTR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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