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Contents

README

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L5991AD

STMicroelectronics · AC-DC Controllers And Regulators · SOIC-16

L5991AD from STMicroelectronics, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SYNC bidirectional Synchronization pin operating as clock output in master mode (7mA typical source capability, 4V amplitude) or edge-triggered slave input for external frequency synchronization.
2 RCT bidirectional Oscillator timing node connected to external RC network for frequency control; internal circuit charges and discharges timing capacitor between 1V valley and 3V peak.
3 DC input Duty cycle control input; voltage 1-3V sets maximum duty cycle between 0% and upper limit Dx, <1V inhibits output, floating or >3V selects maximum.
4 VREF power_out 5.0V±1.5% reference voltage output (0.4mV/°C temperature coefficient, 2mV line regulation, 2mV load regulation at 1-10mA output current).
5 VFB input Error amplifier inverting input for feedback signal; compared to internal 2.5V reference with 60-90dB open-loop gain and 1.7-4MHz unity-gain bandwidth.
6 COMP output Error amplifier output for frequency compensation network connection; voltage monitored for standby frequency reduction at light load.
7 SS output Soft-start control pin; external capacitor charged by 14-26µA current source (at 25°C) ramping to 7V clamp voltage for smooth power-up.
8 VCC power_in Signal circuit supply; 7.8-9V startup threshold (L5991A) with 7-8.2V minimum operating voltage (L5991A) and internal 25V zener clamp.
9 VC power_in Power stage driver supply that absorbs pulsed current when driving external switch gate; buffer capacitor recommended near IC.
10 OUT output Totem-pole driver output to external power switch; 1.6A peak source (NPN Darlington), 2A peak sink (VDMOS), 13V internal gate clamp, 20-100ns rise/fall time.
11 PGND power_in Power ground; return path for pulsed gate drive current loop to external switch.
12 SGND power_in Signal ground; reference point for all control circuitry and external control signal returns.
13 ISEN input Current sense input from external resistor hot lead; 100ns internal leading-edge blanking, 1.1-1.3V fault threshold, 2.85-3.15V/V transfer gain.
14 DIS input Device disable control input; threshold >2.5V triggers shutdown with restart requiring VCC below UVLO, must be tied to SGND if unused.
15 DC-LIM input Duty cycle limit control; connection to VREF sets maximum duty cycle to approximately 50%, floating or grounded allows full maximum duty cycle.
16 ST-BY input Standby mode control input; resistor RB to RCT pin sets normal frequency (fosc), connect to VREF or leave floating to enable light-load mode (<13% rated power).

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-16
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: L5991AD
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: l5991ad-etched.step / l5991ad-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l5991ad.step / l5991ad.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (19 pp, sha256 a0e39653f17acfa3, retrieved 2026-10-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF