component
L5973AD
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STMicroelectronics DC-DC Converters, SOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownL5973AD
STMicroelectronics · DC-DC Converters · SOP-8-EP
L5973AD from STMicroelectronics, in a SOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | output | Regulator output, with an absolute DC voltage range of -1 to 40 V (peak -5 to 40 V at 0.1 µs) and output current limited internally. |
| 2 | SYNC | bidirectional | Master/slave synchronization pin: left open it presents a signal synchronous with the internal switch turn-off, and an external signal above 500 kHz synchronizes the device; absolute range -0.3 to 4 V. |
| 3 | INH | input | Active-high inhibit: above 2.2 V the device is off and below 0.8 V it is on, it must be grounded if unused, and an internal pull-up disables the device when open; absolute range -0.3 V to VCC. |
| 4 | COMP | output | Error amplifier output used for frequency compensation, with a high level output voltage of 3.5 V and a low level output voltage of 0.4 V. |
| 5 | FB | input | Step-down feedback input: connecting the output directly gives 1.235 V, otherwise an external divider is required (typically 4.7 kΩ to ground), and the analog pin is rated 4 V. |
| 6 | VREF | power_in | 3.3 V reference voltage output (3.234 V to 3.366 V at IREF = 0 to 5 mA) that needs no filter capacitor for stability. |
| 7 | GND | power_in | Ground pin for the device. |
| 8 | VCC | power_in | Unregulated DC input voltage, with an operating range of 4 V to 36 V and an absolute maximum input voltage of 40 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage | V8 | 40 | V | 4 | |||
| Output DC voltage | V1 | -1 | 40 | V | 4 | ||
| Output peak voltage | V1 | -5 | 40 | V | t = 0.1 μs | 4 | |
| Analog pins | V4, V5 | 4 | V | 4 | |||
| INH voltage | V3 | -0.3 | V | upper limit VCC | 4 | ||
| SYNC voltage | V2 | -0.3 | 4 | V | 4 | ||
| Power dissipation | PTOT | 2.25 | W | TA ≤ 60 °C | 4 | ||
| Operating junction temperature range | TJ | -40 | 150 | °C | 4 | ||
| Storage temperature range | TSTG | -55 | 150 | °C | 4 | ||
| Maximum thermal resistance junction-ambient | RthJA | 40 | °C/W | package mounted on board | 4 | ||
| Operating input voltage range | VCC | 4 | 36 | V | Vo = 1.235 V; Io = 2 A | 5 | |
| MOSFET on resistance | RDS(on) | 0.25 | 0.5 | Ω | 5 | ||
| Maximum limiting current | Il | 2 | 2.3 | 3.5 | A | VCC = 4.4 V to 36 V | 5 |
| Switching frequency | fs | 500 | kHz | 5 | |||
| Duty cycle | 0 | 100 | % | 5 | |||
| Voltage feedback | V5 | 1.22 | 1.235 | 1.25 | V | 4.4 V < VCC < 36 V, 20 mA < IO < 2 A | 5 |
| Efficiency | η | 90 | % | VO = 5 V, VCC = 12 V | 5 | ||
| Total operating quiescent current | Iqop | 5 | 7 | mA | 5 | ||
| Quiescent current | Iq | 2.7 | mA | Duty cycle = 0; VFB = 1.5 V | 5 | ||
| Total stand-by quiescent current | Iqst-by | 50 | 100 | μA | Vinh > 2.2 V | 5 | |
| INH threshold voltage device ON | 0.8 | V | Device ON | 5 | |||
| INH threshold voltage device OFF | 2.2 | V | Device OFF | 5 | |||
| High level output voltage | VOH | 3.5 | V | VFB = 1 V | 5 | ||
| Low level output voltage | VOL | 0.4 | V | VFB = 1.5 V | 5 | ||
| Source output current | Io source | 200 | 300 | μA | VCOMP = 1.9 V; VFB = 1 V | 5 | |
| Sink output current | Io sink | 1 | 1.5 | mA | VCOMP = 1.9 V; VFB = 1.5 V | 5 | |
| Source bias current | Ib | 2.5 | 4 | μA | 5 | ||
| DC open loop gain | 50 | 57 | dB | RL = ∞ | 5 | ||
| Transconductance | gm | 2.3 | mS | Icomp = -0.1 mA to 0.1mA; VCOMP = 1.9 V | 6 | ||
| Sync high input voltage | 2.5 | V | VCC = 4.4 V to 36 V | 6 | |||
| Sync low input voltage | 0.74 | V | VCC = 4.4 V to 36 V | 6 | |||
| Slave sink current | 0.11 | 0.21 | mA | Vsync = 0.74 V (1) | 6 | ||
| Slave sink current | 0.25 | 0.45 | mA | Vsync = 2.33 V | 6 | ||
| Master output amplitude | 2.75 | 3 | V | Isource = 3 mA | 6 | ||
| Output pulse width | 0.2 | 0.35 | μs | no load, Vsync = 1.65 V | 6 | ||
| Reference voltage | VREF | 3.234 | 3.3 | 3.366 | V | IREF = 0 to 5 mA | 6 |
| Reference voltage | VREF | 3.2 | 3.3 | 3.399 | V | IREF = 0 to 5 mA; VCC = 4.4 V to 36 V | 6 |
| Line regulation | 5 | 10 | mV | IREF = 0 mA; VCC = 4.4 V to 36 V | 6 | ||
| Load regulation | 8 | 15 | mV | IREF = 0 to 5 mA | 6 | ||
| Short circuit current | 10 | 18 | 30 | mA | 6 |
CAD (KiCad official)
- Symbol:
L5973AD - Footprint:
Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm - 3D model: SOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
l5973ad-etched.step/l5973ad-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);l5973ad.step/l5973ad.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (22 pp, sha256
5657968dab13e305, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).