# L5970ADTR

**STMicroelectronics** · DC-DC Converters · SOIC-8

L5970ADTR from STMicroelectronics, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated step-down converter output; delivers up to 1.5A DC current to load, output voltage adjustable from 1.235V to 35V depending on external feedback divider network. |
| 2 | SYNC | bidirectional | Master/Slave synchronization pin; outputs signal synchronous with internal power turn-off at 500kHz when open, accepts external signal above 500kHz for device synchronization, acts as master or slave when connected with other devices. |
| 3 | INH | input | Active-high inhibit control input; disables device when above 2.2V (OFF state), enables when below 0.8V (ON state), must be grounded if unused or will be disabled by internal pull-up when floating. |
| 4 | COMP | output | Error amplifier output connected to external compensation network; sets loop response and stability characteristics of the voltage feedback control loop. |
| 5 | FB | input | Feedback input for output voltage regulation; direct connection to output sets 1.235V output voltage, external resistor divider with typical 4.7kΩ resistor to ground required for output voltages up to 35V. |
| 6 | VREF | power_out | 3.3V reference voltage output supplying internal circuitry; provides stable 3.234-3.366V output across 4.4-36V input range with no filter capacitor required for stability. |
| 7 | GND | power_in | Ground; common return path for all internal circuits and external connections. |
| 8 | VCC | power_in | Unregulated DC input voltage supply; accepts 4.4V to 36V input range for operation of internal voltage regulator and 1.5A internal P-DMOS power switch. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating input voltage range | VCC | 4.4 |  | 36 | V |  | 3 |
| Output DC voltage | V1 | -1 |  | 40 | V |  | 2 |
| Output peak voltage | V1 | -5 |  | 40 | V | t = 0.1µs | 2 |
| Input voltage | V8 |  |  | 40 | V |  | 2 |
| Analog pins | V4, V5 |  |  | 4 | V |  | 2 |
| SYNC pin voltage | V2 | -0.3 |  | 4 | V |  | 2 |
| Power dissipation | Ptot |  |  | 0.75 | W | Tamb ≤ 60°C | 2 |
| Operating junction temperature range | Tj | -40 |  | 150 | °C |  | 2 |
| Storage temperature range | Tstg | -55 |  | 150 | °C |  | 2 |
| Thermal resistance junction to ambient | Rth (j-amb) |  |  | 120 | °C/W | Package mounted on board | 2 |
| Mosfet on resistance | RDSON |  | 0.25 | 0.5 | Ω |  | 3 |
| Maximum limiting current | Il |  | 1.8 |  | A | VCC = 4.4V to 36V | 3 |
| Switching frequency | fs |  | 500 |  | KHz |  | 3 |
| Duty cycle |  | 0 |  | 100 | % |  | 3 |
| Voltage feedback | V5 | 1.22 | 1.235 | 1.25 | V | 4.4V < VCC < 36V | 3 |
| Efficiency | η |  | 90 |  | % | VO = 5V, VCC = 12V | 3 |
| Total operating quiescent current | Iqop |  | 5 | 7 | mA |  | 3 |
| Quiescent current | Iq |  | 2.7 |  | mA | Duty Cycle = 0; VFB = 1.5V | 3 |
| Total stand-by quiescent current | Iqst-by |  | 50 | 100 | µA | Vinh > 2.2V | 3 |
| INH threshold voltage, device ON | INH |  |  | 0.8 | V | Device ON | 3 |
| INH threshold voltage, device OFF | INH | 2.2 |  |  | V | Device OFF | 3 |
| High level output voltage | VOH | 3.5 |  |  | V | VFB = 1V | 3 |
| Low level output voltage | VOL |  |  | 0.4 | V | VFB = 1.5V | 3 |
| Source output current | Io source | 200 |  | 300 | µA | VCOMP = 1.9V; VFB = 1V | 3 |
| Sink output current | Io sink | 1 |  | 1.5 | mA | VCOMP = 1.9V; VFB = 1.5V | 3 |
| Source bias current | Ib | 2.5 |  | 4 | µA |  | 3 |
| DC open loop gain |  | 50 | 57 |  | dB | RL = ∞ | 3 |
| Transconductance | gm |  | 2.3 |  | mS | Icomp = -0.1mA to 0.1mA; VCOMP = 1.9V | 3 |
| SYNC high input voltage |  | 2.5 |  |  | V | VCC = 4.4V to 36V | 3 |
| SYNC low input voltage |  |  |  | 0.74 | V | VCC = 4.4V to 36V | 3 |
| Slave sink current |  | 0.11 |  | 0.25 | mA | Vsync = 0.74V (guaranteed by design) | 3 |
| Slave sink current |  | 0.21 |  | 0.45 | mA | Vsync = 2.33V | 3 |
| Master output amplitude |  | 2.75 | 3 |  | V | Isource = 3mA | 3 |
| Output pulse width |  | 0.2 |  | 0.35 | µs | no load, Vsync = 1.65V | 3 |
| Reference voltage |  | 3.234 | 3.3 | 3.366 | V | IREF = 0 to 5mA | 3 |
| Reference voltage |  | 3.2 | 3.3 | 3.399 | V | IREF = 0 to 5mA; VCC = 4.4V to 36V | 3 |
| Line regulation |  |  | 5 | 10 | mV | IREF = 0mA; VCC = 4.4V to 36V | 3 |
| Load regulation |  |  | 8 | 15 | mV | IREF = 0 to 5mA | 3 |
| Short circuit current |  | 10 | 18 | 30 | mA |  | 3 |

## CAD (KiCad official)

- Symbol: `L5970ADTR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `l5970adtr-etched.step` / `l5970adtr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l5970adtr.step` / `l5970adtr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588912459784589312) (11 pp, sha256 `cf023a59e3ab8e46`, retrieved 2026-09-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l5970adtr-datasheet.pdf)