component
L4981BD
Public Made by Adomby adom
STMicroelectronics AC-DC Controllers & Regulators, SOIC-20-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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L4981BD
STMicroelectronics · AC-DC Controllers & Regulators · SOIC-20-300mil
L4981BD from STMicroelectronics, in a SOIC-20-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P-GND | power_in | Power ground return for the gate driver and power stage, kept separate from signal ground S-GND (pin 10). |
| 2 | IPK | input | Peak current limit input for the L4981B, set by two external resistors between the sense resistor, pin 2 and the reference voltage; pin 2 is limited to -0.3 to 5.5 V (-2 V for 1 µs). |
| 3 | OVP | input | Overvoltage protection comparator input, compared against an internal 5.1 V (typ) reference via a divider from the boost output. |
| 4 | IAC | input | AC current input carrying a current proportional to the rectified mains voltage, rated at 5 mA maximum. |
| 5 | CA-OUT | output | Current amplifier output; an external RC network sets the current loop gain. |
| 6 | LFF | input | Load feedforward input, best controlled between 1.5 V and 5.3 V; connect to VREF (pin 11) if unused. |
| 7 | VRMS | input | Input for the proportional RMS line voltage, best controlled between 1.5 V and 5.5 V; connect to VREF (pin 11) if unused. |
| 8 | MULT-OUT | input | Multiplier output shared with the current amplifier input; a high-impedance node that must not be taken below -0.5 V. |
| 9 | ISENSE | input | Current amplifier inverting input that must not be driven below -0.5 V. |
| 10 | S-GND | power_in | Signal ground reference for the control circuitry, separate from power ground P-GND (pin 1). |
| 11 | VREF | power_out | Precise ±2% reference output of 5.1 V (typ) that is internally current limited and can deliver up to 10 mA. |
| 12 | SS | passive | Soft start capacitor pin; an internal 100 µA (typ) source charges the external capacitor, which is discharged during overvoltage and UVLO conditions. |
| 13 | VA-OUT | output | Error amplifier output for which an RC network sets the voltage loop gain; the absolute maximum is 8.5 V. |
| 14 | VFEED | input | Voltage error amplifier inverting input, fed through a divider from the boost output voltage. |
| 15 | P-UVLO | input | Programmable undervoltage lockout threshold input, set by a divider between VCC and GND (for example 220K to VCC and 33K to GND gives about 12 V turn-on). |
| 16 | FREQ-MOD | bidirectional | On the L4981B this is the frequency modulation current input, with a resistor to the rectified line; the L4981A uses it as a CMOS-compatible SYNC input/output, and the absolute maximum is 7 V. |
| 17 | ROSC | passive | An external resistor to ground sets the constant charging current of COSC; the pin voltage is rated -0.3 to 3 V. |
| 18 | COSC | passive | An external capacitor to GND sets the switching frequency; the input sink current is rated at 15 mA. |
| 19 | VCC | power_in | Supply input, rated at 19.5 V maximum operating supply voltage with a self-limiting zener (20 to 30 V) and an absolute maximum of 50 mA ICC. |
| 20 | GDRV | output | Gate driver output using a bipolar and DMOS totem pole stage that can deliver peak current in excess of 1 A to drive a MOSFET or IGBT, with a peak sink of 2 A and a source of 1.5 A. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SOIC-20-300mil |
| Category | Power Management ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Output peak current sink | IGDRV | 2 | A | t = 1µs | 2 | ||
| Output peak current source | IGDRV | 1.5 | A | t = 1µs | 2 | ||
| Gate driver output voltage | VGDRV | -1 | V | t = 0.1µs | 2 | ||
| Voltages at pins 3, 14, 7, 6, 12, 15 | -0.3 | 9 | V | 2 | |||
| Error amplifier voltage | VVA-OUT | -0.3 | 8.5 | V | pin 13 | 2 | |
| AC input current | IAC | 5 | mA | pin 4 | 2 | ||
| Voltages at pins 8, 9 | -0.5 | 7 | V | 2 | |||
| Current amplifier output voltage | VCA-OUT | -0.3 | 8.5 | V | Isource = -20mA; Isink = 20mA | 2 | |
| Voltage at pin 17 | VROSC | -0.3 | 3 | V | pin 17 | 2 | |
| Voltage at pins 11, 18 | -0.3 | 7 | V | 2 | |||
| Input sink current | ICOSC | 15 | mA | pin 18 | 2 | ||
| Frequency modulation sink current (L4981B) | IFREQ-MOD | 5 | mA | pin 16 | 2 | ||
| Voltage at pin 2 | VIPK | -0.3 | 5.5 | V | pin 2 | 2 | |
| Voltage at pin 2 transient | VIPK | -2 | V | t = 1µs | 2 | ||
| Power dissipation SO20 | Ptot | 0.6 | W | Tamb = 70°C | 2 | ||
| Top operating ambient temperature | Top | -40 | 125 | °C | 2 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 2 | ||
| Input offset voltage | VIO | -8 | 8 | mV | -25°C < TJ < 85°C | 4 | |
| Input bias current | IIB | -500 | -50 | 500 | nA | VFEED = 0V | 4 |
| Open loop gain (error amplifier) | 70 | 100 | dB | 4 | |||
| Output high voltage | V13H | 5.5 | 6.5 | 7.5 | V | VFEED = 4.7V; IVA-OUT = -0.5mA | 4 |
| Output low voltage | V13L | 0.4 | 1 | V | VFEED = 5.5V; IVA-OUT = 0.5mA | 4 | |
| Output source current | -I13 | 2 | 10 | mA | VFEED = 4.7V; VVA-OUT = 3.5V | 4 | |
| Output sink current | I13 | 4 | 20 | mA | VFEED = 5.5V; VVA-OUT = 3.5V | 4 | |
| Reference output voltage | Vref | 4.97 | 5.1 | 5.23 | V | -25°C < TJ < 85°C | 4 |
| Reference output voltage at 25°C | Vref | 5.01 | 5.1 | 5.19 | V | Tj = 25°C; Iref = 0 | 4 |
| Load regulation | ΔVref | 3 | 15 | mV | 1mA ≤ Iref ≤ 10mA; -25°C < TJ < 85°C | 4 | |
| Line regulation | ΔVref | 3 | 10 | mV | 12V ≤ VCC ≤ 19V; -25°C < TJ < 85°C | 4 | |
| Short circuit current | Iref sc | 20 | 30 | 50 | mA | Vref = 0V | 4 |
| Initial accuracy | fosc | 85 | 100 | 115 | KHz | Tj = 25°C | 4 |
| Frequency stability | 80 | 100 | 120 | KHz | 12V ≤ VCC ≤ 19V; -25°C < TJ < 85°C | 4 | |
| Ramp valley to peak | Vsvp | 4.7 | 5 | 5.3 | V | 4 | |
| Charge current | I18C | 0.45 | 0.55 | 0.65 | mA | VCOSC = 3.5V | 4 |
| Discharge current | I18D | 11.5 | mA | VCOSC = 3.5V | 4 | ||
| Ramp valley voltage | V18 | 0.9 | 1.15 | 1.4 | V | 4 | |
| Maximum oscillation frequency | f18max | 85 | 100 | 115 | KHz | VFREQ-MOD = 0V (Pin 16); Ifreq = 0 | 4 |
| Minimum oscillator frequency | f18min | 74 | KHz | IFREQ-MOD = 360µA (Pin 16); VVRMS = 4V (Pin 7) | 4 | ||
| Soft start source current | ISS | 60 | 100 | 140 | µA | VSS = 3V | 4 |
| Soft start output saturation voltage | V12sat | 0.1 | 0.25 | V | V3 = 6V; ISS = 2mA | 4 | |
| Operating supply voltage | VCC | 19.5 | V | 5 | |||
| Overvoltage rising threshold | Vthr | 5.1 | V | min Vref-20mV; max Vref+20mV | 5 | ||
| Overvoltage hysteresis | V3Hys | 180 | 250 | 320 | mV | 5 | |
| Overvoltage propagation delay | td | 1 | 2 | µs | VOVP = Vthr + 100mV | 5 | |
| Overcurrent threshold voltage | Vth | -30 | 30 | mV | 5 | ||
| Overcurrent propagation delay | td | 0.4 | 0.9 | µs | VOCP = Vthr - 0.2V | 5 | |
| Leakage current (L4981B) | IL | 5 | µA | VIPK = -0.1V | 5 | ||
| Current amplifier input offset voltage | Voffset | -2 | 2 | mV | VMULT OUT = VSENSE = 3.5V | 5 | |
| Current amplifier input bias current | I9bias | -500 | 50 | 500 | nA | VSENSE = 0V | 5 |
| Current amplifier open loop gain | 70 | 100 | dB | 1.1V ≤ VCA OUT ≤ 6V | 5 | ||
| Supply voltage rejection | SVR | 68 | 90 | dB | 12V ≤ VCC ≤ 19V; VMULT OUT = 3.5V; VSENSE = 3.5V | 5 | |
| Current amplifier output high voltage | V5H | 6.2 | V | VMULT OUT = 200mV; ICA OUT = -0.5mA; VIAC = 0V | 5 | ||
| Current amplifier output low voltage | V5L | 0.9 | V | VMULT OUT = -200mV; ICA OUT = 0.5mA; VIAC = 0V | 5 | ||
| Output source current | -I5 | 2 | 10 | mA | VMULT OUT = 200mV; VIAC = 0V; VCA-OUT = 3.5V | 5 | |
| Output sink current | I5 | 2 | 10 | mA | 5 | ||
| Output voltage low | V20L | 0.5 | 0.8 | V | ISINK = 250mA | 5 | |
| Output voltage high | V20H | 11.5 | 12.5 | V | ISOURCE = 250mA; VCC = 15V | 5 | |
| Supply current before start up | I19start | 0.3 | 0.5 | mA | VCC = 14V | 5 | |
| Operating supply current | I19 | 12 | 16 | mA | Pin20 = 1nF | 5 | |
| Turn on threshold | Vth ON | 14.5 | 15.5 | 16.5 | V | 5 | |
| Thermal resistance junction-ambient SO20 | Rth j-amb | 120 | °C/W | SO 20 package | 3 |
CAD (KiCad official)
- Symbol:
L4981BD - Footprint:
Package_SO:SOIC-20W_7.5x12.8mm_P1.27mm - 3D model: SOIC-20-300mil (KiCad packages3D, STEP)
- 3D model files:
l4981bd-etched.step/l4981bd-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);l4981bd.step/l4981bd.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (16 pp, sha256
607996fde19865e3, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).