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L4973V5.1

Public Made by Adom

by adom

STMicroelectronics DC-DC Converters, DIP-18. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Ray l4973v5-1: specified limits as data (metadata.characteristics, 60 rows from the datasheet) b1b09ca 17d ago

L4973V5.1

STMicroelectronics · DC-DC Converters · DIP-18

L4973V5.1 from STMicroelectronics, in a DIP-18. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OSC passive An external resistor from the unregulated input voltage to pin 1 and a capacitor from pin 1 to ground set the switching frequency; line feed forward is obtained automatically.
2 OUT power_out Step-down regulator output; absolute maximum output DC voltage is -1 V and output peak voltage is -5 V at t = 0.1 µs, f = 200 kHz.
3 OUT power_out Step-down regulator output; absolute maximum output DC voltage is -1 V and output peak voltage is -5 V at t = 0.1 µs, f = 200 kHz.
4 GND power_in Signal ground.
5 GND power_in Signal ground.
6 GND power_in Signal ground.
7 VCC power_in Unregulated DC input voltage; operating range is 8 V to 55 V and absolute maximum input voltage is 58 V.
8 VCC power_in Unregulated DC input voltage; operating range is 8 V to 55 V and absolute maximum input voltage is 58 V.
9 BOOT passive A capacitor connected between this pin and the output drives the internal D-MOS; the datasheet gives a bootstrap voltage rating of 70 V and V9-V8 of 14 V.
10 INH input Active-high logic inhibit that disables the device (sleep mode); high level is 3.0 V min and low level is 0.8 V max, and it must be connected to GND if not used since floating disables the device.
11 COMP passive Error amplifier output used for frequency compensation; its output swings from 0.65 V (low) to 11.0 V (high).
12 VFB input Step-down feedback input; connecting the output directly to this pin gives 5.1 V for the L4973V5.1, and an external resistive divider is required for higher output voltages.
13 GND power_in Signal ground.
14 GND power_in Signal ground.
15 GND power_in Signal ground.
16 V5.1 power_out Externally available precise 5.1 V reference, specified at 5.025 V to 5.175 V (typ 5.1 V) for Iref = 0 to 20 mA.
17 SS passive Soft-start pin; the datasheet specifies a soft-start charge current of 30 to 60 µA and discharge current of 15 to 30 µA.
18 SYNC bidirectional Input/output synchronization pin; high input level is 3.5 V min and low input level is 0.9 V max for VCC = 8 V to 55 V.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DIP-18
Category Power Management (PMIC)
Pins 18

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range 8 55 V VO = VREF to 40 V; IO = 3.5A 6
Output voltage (L4973V5.1) 5.05 5.1 5.15 V IO = 1 A 6
Output voltage (L4973V5.1) 5 5.1 5.2 V IO = 0.5 A to 3.5 A; VCC = 8 V to 55 V 6
Output voltage (L4973V5.1) 4.95 5.1 5.25 V (2) specifications referred to TJ -40 °C to 125 °C 6
RDS(on) RDS(on) 0.15 0.22 Ω VCC = 10.5 V; IO = 3.5 A 6
RDS(on) RDS(on) 0.35 Ω (2) specifications referred to TJ -40 °C to 125 °C 6
Maximum limiting current 3.8 4.5 5.5 A VCC = 8 V to 55 V; (2) 6
Maximum limiting current 4 4.5 5.5 A VCC = 8 V to 55 V 6
Switching frequency 90 100 110 kHz (2) specifications referred to TJ -40 °C to 125 °C 6
Supply voltage ripple rejection 60 dB Vi = VCC+2 VRMS; VO = Vref; IO = 1 A; fripple = 100 Hz 6
Switching frequency stability vs. supply voltage Δfsw 2 5 % VCC = 8 V to 55 V 6
Reference voltage VREF 5.025 5.1 5.175 V Iref = 0 to 20 mA; VCC = 8 to 55 V 6
Reference voltage VREF 4.95 5.1 5.25 V (2) specifications referred to TJ -40 °C to 125 °C 6
Line regulation 5 10 mV Iref = 0 mA; VCC = 8 to 55 V 6
Load regulation 2 6 mV Vref = 0 to 5 mA 6
Load regulation 10 25 mV VCC = 0 to 20 mA 6
Short circuit current 30 65 100 mA 6
Soft-start charge current 30 45 60 μA 7
Soft-start discharge current 15 22 30 μA 7
Inhibit high level voltage 3 V (2) specifications referred to TJ -40 °C to 125 °C 7
Inhibit low level voltage 0.8 V (2) specifications referred to TJ -40 °C to 125 °C 7
Isource high level 10 16 50 μA VINH = 3 V; (2) 7
Isource low level 10 15 50 μA VINH = 0.8 V; (2) 7
Total operating quiescent current 4 6 mA Duty cycle = 50 % 7
Quiescent current 2.7 4 mA Duty cycle = 0 7
Total stand-by quiescent current 100 200 μA VCC = 24 V; VINH = 5 V 7
Total stand-by quiescent current 150 300 μA VCC = 55 V; VINH = 5 V 7
Error amplifier high level output voltage 11 V 7
Error amplifier low level output voltage 0.65 V 7
Source bias current 1 2 3 μA 7
Source output current 200 300 600 μA 7
Sink output current 200 300 μA 7
Error amplifier supply voltage ripple rejection 60 80 dB VCOMP = VFB; CREF = 4.7 μF; 1-5 mA load current 7
Error amplifier DC open loop gain 50 60 dB RL = ∞ 7
Error amplifier transconductance 2.5 mS Icomp = -0.1 to 0.1 mA; Vcomp = 6 V 7
Ramp valley 0.78 0.85 0.92 V 7
Ramp peak 1.9 2.1 2.3 V VCC = 8 V 7
Ramp peak 9 9.6 10.2 V VCC = 55 V 7
Maximum duty cycle 95 97 % 7
Sync high input voltage 3.5 V VCC = 8 V to 55 V 8
Sync low input voltage 0.9 V VCC = 8 V to 55 V 8
Slave sink current 0.15 0.25 0.45 mA 8
Master output amplitude 4 4.5 V Isource = 3 mA 8
Sync output pulse width 0.2 0.35 μs No load; Vsync = 4.5 V 8
Input voltage (DIP-18 pin 7,8) V7,V8 58 V 5
Output DC voltage (DIP-18 pin 2,3) V2,V3 -1 V 5
Output peak voltage (DIP-18 pin 2,3) -5 V t = 0.1 μs; f = 200 kHz 5
Bootstrap voltage (parameter label not printed in table) V9-V8 14 V 5
Bootstrap voltage V9,V10 70 V 5
Analog input voltage (DIP-18 pin 11) V11 12 V VCC = 24 V 5
Analog input voltage (DIP-18 pin 17) V17 13 V VCC = 24 V 5
Analog input voltage (DIP-18 pin 12) V12 -0.3 6 V VCC = 20 V 5
Analog input voltage (DIP-18 pin 18) V18 0.3 5.5 V VCC = 20 V 5
Inhibit voltage (DIP-18 pin 10) V10 -0.3 V 5
Power dissipation Ptot 5 W DIP; Tpins ≤ 90 °C 5
Power dissipation Ptot 1.3 W DIP; TA = 70 °C; no copper area 5
Power dissipation Ptot 2 W DIP; TA = 70 °C; 4 cm² copper area on PCB 5
Junction and storage temperature TJ,TSTG -40 150 °C 5
Maximum thermal resistance junction-pin RthJP 12 °C/W DIP-18 5
Maximum thermal resistance junction-ambient RthJA 60 °C/W DIP-18; package mounted on board (note 1) 5

CAD (KiCad official)

  • Symbol: L4973V5.1
  • Footprint: Package_DIP:DIP-18_W7.62mm
  • 3D model: DIP-18 (KiCad packages3D, STEP)
  • 3D model files: l4973v5-1-etched.step / l4973v5-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l4973v5-1.step / l4973v5-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (28 pp, sha256 8bad7b96ec4d871a, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF