component
L4949EDTR-E
Public Made by Adomby adom
STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 2d ago |
| viewers | 2d ago |
| l4949edtr-e-etched.glb | 2d ago |
| l4949edtr-e-etched.step | 2d ago |
| l4949edtr-e-hero.glb | 2d ago |
| l4949edtr-e-hero.overlay.json | 2d ago |
| l4949edtr-e.glb | 2d ago |
| l4949edtr-e.kicad_mod | 2d ago |
| l4949edtr-e.kicad_sym | 2d ago |
| l4949edtr-e.lbr | 2d ago |
| l4949edtr-e.step | 2d ago |
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| README.md | 2d ago |
L4949EDTR-E
STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SO-8
L4949EDTR-E from STMicroelectronics, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VS | power_in | Supply input voltage ranging from 5V to 28V; must be blocked to GND via external capacitor. |
| 2 | SI | input | Sense input for monitoring input voltage; connect via external voltage divider to VS and GND. |
| 3 | VZ | power_out | Preregulator output voltage stabilized to 5V with maximum output current of 10 µA. |
| 4 | CT | input | Reset pulse delay adjustment pin; connect external capacitor to GND to set delay time. |
| 5 | GND | power_in | Ground reference, common return path. |
| 6 | RES | output | Reset output (open-drain) pulled low when output voltage drops below 4.5V threshold. |
| 7 | SO | output | Sense output (open-drain) pulled low when sense input voltage drops below 1.23V threshold. |
| 8 | VOUT | power_out | Regulated output voltage nominally 5V with ±1% accuracy at 1 mA load; block to GND via external capacitor. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | STMicroelectronics |
| Package | SO-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
L4949EDTR-E - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
l4949edtr-e-etched.step/l4949edtr-e-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);l4949edtr-e.step/l4949edtr-e.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: STMicroelectronics datasheet (19 pp, sha256
eb565c8e521260c1, retrieved 2026-10-03, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).