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Contents

README

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L2SA812RLT1G

LRC · Bipolar (BJT) · SOT-23

L2SA812RLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BASE input Base terminal of the PNP transistor; the datasheet's maximum emitter-base voltage is VEBO -6 V.
2 EMITTER passive Emitter terminal; the datasheet's maximum emitter-base voltage is VEBO -6 V and the emitter current limit is the -150 mAdc continuous collector current rating.
3 COLLECTOR passive Collector terminal; the datasheet rates VCEO -50 V, VCBO -60 V and continuous collector current IC -150 mAdc.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-23
Category Transistors/Thyristors
Pins 3

CAD (KiCad official)

  • Symbol: L2SA812RLT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: l2sa812rlt1g-etched.step / l2sa812rlt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l2sa812rlt1g.step / l2sa812rlt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (5 pp, sha256 20876a594b5335d3, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF