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L2N7002WT1G

Public Made by Adom

by adom

LRC MOSFETs, SOT-323. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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l2n7002wt1g-etched.step l2n7002wt1g: factory component page (tier=lcsc) · Ray 29d ago
l2n7002wt1g-hero.glb l2n7002wt1g: hero GLB from the etched model (keeps the MPN mark) · Ray 29d ago
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page.json l2n7002wt1g: specified limits as data (metadata.characteristics, 34 rows from the datasheet) · Ray 24d ago
README.md l2n7002wt1g: specified limits as data (metadata.characteristics, 34 rows from the datasheet) · Ray 24d ago

L2N7002WT1G

LRC · MOSFETs · SOT-323

L2N7002WT1G from LRC, in a SOT-323. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate of the N-channel MOSFET; the datasheet limits gate-source voltage to ±20 V continuous and ±40 V non-repetitive (tp ≤ 50 µs), with 1000 V ESD protection.
2 Source passive Source of the N-channel MOSFET; the body diode continuous source current is rated at −115 mA and pulsed at −800 mA.
3 Drain passive Drain of the N-channel MOSFET; rated at 60 V drain-source voltage with continuous drain current of 115 mA at TC = 25°C (75 mA at TC = 100°C) and 800 mA pulsed.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-323
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain–Source Voltage VDSS 60 Vdc 1
Drain–Gate Voltage VDGR 60 Vdc RGS = 1.0 MΩ 1
Drain Current – Continuous ID -115 115 mAdc TC = 25°C (Note 1.) 1
Drain Current – Continuous ID -75 75 mAdc TC = 100°C (Note 1.) 1
Drain Current – Pulsed IDM -800 800 mAdc Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0% (Note 2.) 1
Gate–Source Voltage – Continuous VGS -20 20 Vdc 1
Gate–Source Voltage – Non-repetitive VGSM -40 40 Vpk tp ≤ 50 µs 1
Total Device Dissipation, FR–5 Board PD 225 mW TA = 25°C (Note 3.) 1
Derate above 25°C, FR–5 Board PD 1.8 mW/°C Derate above 25°C (FR–5 Board) 1
Thermal Resistance, Junction to Ambient, FR–5 Board RθJA 556 °C/W FR–5 Board (Note 3.) 1
Total Device Dissipation, Alumina Substrate PD 300 mW Alumina Substrate (Note 4.), TA = 25°C 1
Derate above 25°C, Alumina Substrate PD 2.4 mW/°C Derate above 25°C (Alumina Substrate) 1
Thermal Resistance, Junction to Ambient, Alumina Substrate RθJA 417 °C/W Alumina Substrate (Note 4.) 1
Junction and Storage Temperature TJ, Tstg -55 150 °C 1
Drain–Source Breakdown Voltage V(BR)DSS 60 Vdc VGS = 0, ID = 10 µAdc 2
Zero Gate Voltage Drain Current, TJ = 25°C IDSS 1 µAdc VGS = 0, VDS = 60 Vdc, TJ = 25°C 2
Zero Gate Voltage Drain Current, TJ = 125°C IDSS 500 µAdc VGS = 0, VDS = 60 Vdc, TJ = 125°C 2
Gate–Body Leakage Current, Forward IGSSF 1 Adc VGS = 20 Vdc 2
Gate–Body Leakage Current, Reverse IGSSR -1 µAdc VGS = –20 Vdc 2
Gate Threshold Voltage VGS(th) 1 1.6 2.5 Vdc VDS = VGS, ID = 250 µAdc 2
On–State Drain Current ID(on) 500 mA VDS ≥ 2.0 VDS(on), VGS = 10 Vdc 2
Static Drain–Source On–State Voltage VDS(on) 3.75 Vdc VGS = 10 Vdc, ID = 500 mAdc 2
Static Drain–Source On–State Voltage VDS(on) 0.375 Vdc VGS = 5.0 Vdc, ID = 50 mAdc 2
Static Drain–Source On–State Resistance rDS(on) 7.5 Ohms VGS = 10 V, ID = 500 mAdc, TC = 25°C 2
Static Drain–Source On–State Resistance rDS(on) 13.5 Ohms VGS = 10 V, ID = 500 mAdc, TC = 125°C 2
Forward Transconductance gFS 80 mmhos VDS ≥ 2.0 VDS(on), ID = 200 mAdc 2
Input Capacitance Ciss 17 50 pF VDS = 25 Vdc, VGS = 0, f = 1.0 MHz 2
Output Capacitance Coss 10 25 pF VDS = 25 Vdc, VGS = 0, f = 1.0 MHz 2
Reverse Transfer Capacitance Crss 2.5 5 pF VDS = 25 Vdc, VGS = 0, f = 1.0 MHz 2
Turn–On Delay Time td(on) 7 20 ns VDD = 25 Vdc, ID 500 mAdc 2
Turn–Off Delay Time td(off) 11 40 ns RG = 25 Ω, RL = 50 Ω, Vgen = 10 V 2
Diode Forward On–Voltage VSD -1.5 Vdc IS = 115 mAdc, VGS = 0 V 2
Source Current Continuous (Body Diode) IS -115 mAdc 2
Source Current Pulsed ISM -800 mAdc 2

CAD (KiCad official)

  • Symbol: L2N7002WT1G
  • Footprint: Package_TO_SOT_SMD:SOT-323_SC-70
  • 3D model: SOT-323 (KiCad packages3D, STEP)
  • 3D model files: l2n7002wt1g-etched.step / l2n7002wt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l2n7002wt1g.step / l2n7002wt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (4 pp, sha256 fd7d7d2a79114d55, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF