# L2N7002SWT1G

**LRC** · MOSFETs · SC-70

L2N7002SWT1G from LRC, in a SC-70. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Gate | input | Gate of the N-channel MOSFET, with gate-source voltage limited to ±20 V and ESD protected (2000 V HBM). |
| 2 | Source | passive | Source of the N-channel MOSFET, with body-diode source current rated 300 mA. |
| 3 | Drain | passive | Drain of the N-channel MOSFET, rated 60 V drain-source voltage and 320 mA steady-state drain current at TA = 25°C. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SC-70 |
| Category | Transistors/Thyristors |
| Pins | 3 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | VBRDSS | 60 |  |  | V | VGS = 0, ID = 250μA | 2 |
| Gate Threshold Voltage | VGS(th) | 1 |  | 2 | V | VDS = VGS, ID = 250μA | 2 |
| Forward Transconductance | gfs | 80 |  |  | mS | VDS = 5.0 V, ID = 200 mA | 2 |
| Gate-Body Leakage Current, Forward | IGSSF |  |  | 100 | nA | VGS = 20 V | 2 |
| Gate-Source Voltage | VGS | -20 |  | 20 | V |  | 1 |
| Drain-Source Voltage | VDSS |  |  | 60 | V |  | 1 |
| Drain Current | ID |  |  | 320 | mA | Steady state, TA = 25°C | 1 |
| Drain Current | ID |  |  | 230 | mA | Steady state, TA = 85°C | 1 |
| Drain Current | ID |  |  | 380 | mA | t<5s, TA = 25°C | 1 |
| Drain Current | ID |  |  | 270 | mA | t<5s, TA = 85°C | 1 |
| Pulsed Drain Current | IDM |  |  | 1.5 | A | tp = 10μs | 1 |
| Source Current (Body Diode) | IS |  |  | 300 | mA |  | 1 |
| Total Device Dissipation | PD |  |  | 260 | mW | Steady state, Note 1 (FR-4 1.0×0.75×0.062 in.) | 2 |
| Total Device Dissipation | PD |  |  | 417 | mW | t<5s, Note 1 (FR-4 1.0×0.75×0.062 in.) | 2 |
| Junction-to-Ambient Thermal Resistance | RΘJA |  |  | 300 | °C/W | Note 1 (steady-state/t<5s column not resolved) | 2 |
| Junction and Storage Temperature | TJ,Tstg | -55 |  | 150 | °C |  | 1 |
| Lead Temperature for Soldering Purposes | TL |  |  | 260 | °C | 1/8 in from case for 10 s | 2 |
| Gate-Source ESD Rating (HBM) | ESD |  |  | 2000 | V | Method 3015 | 1 |
| Diode Forward On-Voltage | VSD |  | 0.85 |  | V | IS = 0.5 A, VGS = 0 V | 3 |
| Gate Threshold Voltage Temperature Coefficient | VGS(TH)/TJ |  | 4 |  | mV/°C |  | 2 |

## CAD (KiCad official)

- Symbol: `L2N7002SWT1G`
- Footprint: `Package_TO_SOT_SMD:SOT-323_SC-70`
- 3D model: SC-70 (KiCad packages3D, STEP)
- 3D model files: `l2n7002swt1g-etched.step` / `l2n7002swt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l2n7002swt1g.step` / `l2n7002swt1g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588903942087954432) (7 pp, sha256 `09a8250e11828989`, retrieved 2026-11-06, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l2n7002swt1g-datasheet.pdf)