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Contents

README

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L2N7002SLT1G

LRC · MOSFETs · SOT-23

L2N7002SLT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate of the N-channel MOSFET, ESD protected to 2000 V HBM, with VGS limited to ±20 V and threshold VGS(th) of 1.0 V min to 2.0 V (VDS = VGS, ID = 250 µA).
2 Source passive Source of the N-channel MOSFET, also the body-diode anode, with continuous source current (body diode) IS rated 300 mA.
3 Drain passive Drain of the N-channel MOSFET with VDSS of 60 V, ID of 320 mA steady state at TA = 25°C, and 1.5 A pulsed (tp = 10 µs).

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain–Source Voltage VDSS 60 V 1
Gate-Source Voltage VGS -20 20 V 1
Drain Current, steady state ID 320 mA Steady state, TA = 25°C 1
Drain Current, steady state ID 230 mA Steady state, TA = 85°C 1
Drain Current, t<5s ID 380 mA t<5s, TA = 25°C 1
Drain Current, t<5s ID 270 mA t<5s, TA = 85°C 1
Pulsed Drain Current IDM 1.5 A tp = 10μs 1
Source Current (Body Diode) IS 300 mA 1
Total Device Dissipation, steady state PD 300 mW Steady state 2
Total Device Dissipation, t<5s PD 420 mW t<5s 2
Junction-to-Ambient Thermal Resistance, steady state RΘJA 417 ºC/W Steady state 2
Junction-to-Ambient Thermal Resistance, t<5s RΘJA 300 ºC/W t<5s 2
Junction and Storage Temperature TJ,Tstg -55 150 ºC 2
Lead Temperature for Soldering Purposes TL 260 ºC 1/8 in from case for 10 s 2
Gate–Source ESD Rating (HBM, Method 3015) 2000 V HBM, Method 3015 2
Drain–Source Breakdown Voltage VBRDSS 60 V VGS = 0, ID = 250 μA 2
Zero Gate Voltage Drain Current, TJ = 25°C IDSS 1 μA VGS = 0, VDS = 60 V 2
Forward Transconductance gfs 80 mS VDS = 5.0 V, ID = 200 mA 2
Input Capacitance Ciss 35 pF VDS = 25 V, VGS = 0, f = 1.0 MHz 2
Output Capacitance Coss 10 pF VDS = 25 V, VGS = 0, f = 1.0 MHz 2
Reverse Transfer Capacitance Crss 5 pF VDS = 25 V, VGS = 0, f = 1.0 MHz 2

CAD (KiCad official)

  • Symbol: L2N7002SLT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: l2n7002slt1g-etched.step / l2n7002slt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); l2n7002slt1g.step / l2n7002slt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (6 pp, sha256 d553457dda5c662f, retrieved 2026-10-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF