component
L2N7002LT1G
Public Made by Adomby adom
LRC MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+39@@ -0,0 +1,39 @@+# L2N7002LT1G++**LRC** · MOSFETs · SOT-23++L2N7002LT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | GATE | input | Gate of N-channel MOSFET; VGS continuous ±20 V, VGS(th) 1.0-2.0 V at VDS=VGS, ID=250 µA. |+| 2 | SOURCE | passive | Source of N-channel MOSFET and body-diode anode; continuous body-diode source current IS 115 mAdc, pulsed ISM 800 mAdc. |+| 3 | DRAIN | passive | Drain of N-channel MOSFET; VDSS 60 V, continuous ID ±115 mAdc (TC=25 °C), pulsed IDM ±800 mAdc, RDS(on) max 7.5 Ω at VGS=5 V/ID=50 mA. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | LRC |+| Package | SOT-23 |+| Category | Transistors/Thyristors |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `L2N7002LT1G`+- Footprint: `Package_TO_SOT_SMD:SOT-23`+- 3D model: SOT-23 (KiCad packages3D, STEP)+- 3D model files: `l2n7002lt1g-etched.step` / `l2n7002lt1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l2n7002lt1g.step` / `l2n7002lt1g.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586172828182065152) (6 pp, sha256 `1dc34291b20fbdb9`, retrieved 2026-09-18, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-4-6` (text+vision), consensus `claude-opus-4-7` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/l2n7002lt1g-datasheet.pdf)
page.jsonadded+113@@ -0,0 +1,113 @@+{+ "slug": "l2n7002lt1g",+ "version": "0.1.0",+ "type": "component",+ "description": "LRC MOSFETs, SOT-23. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "transistors-thyristors",+ "l2n7002lt1g",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "l2n7002lt1g.kicad_sym",+ "l2n7002lt1g.kicad_mod",+ "l2n7002lt1g.glb",+ "l2n7002lt1g.step",+ "l2n7002lt1g.lbr",+ "docs/hero.png",+ "docs/l2n7002lt1g-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "L2N7002LT1G",+ "manufacturer": "LRC",+ "package": "SOT-23",+ "pin_count": 3,+ "category": "Transistors/Thyristors",+ "subcategory": "MOSFETs",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586172828182065152",+ "parts": {+ "symbol": "l2n7002lt1g.kicad_sym",+ "footprint": "l2n7002lt1g.kicad_mod",+ "model_3d": "l2n7002lt1g-etched.glb",+ "model_3d_plain": "l2n7002lt1g.glb",+ "model_3d_step": "l2n7002lt1g-etched.step",+ "model_3d_step_plain": "l2n7002lt1g.step",+ "lbr": "l2n7002lt1g.lbr"+ },+ "distributor_links": {+ "lcsc": "C12779"+ },+ "pins": [+ {+ "number": "1",+ "name": "GATE",+ "type": "input",+ "description": "Gate of N-channel MOSFET; VGS continuous ±20 V, VGS(th) 1.0-2.0 V at VDS=VGS, ID=250 µA."+ },+ {+ "number": "2",+ "name": "SOURCE",+ "type": "passive",+ "description": "Source of N-channel MOSFET and body-diode anode; continuous body-diode source current IS 115 mAdc, pulsed ISM 800 mAdc."+ },+ {+ "number": "3",+ "name": "DRAIN",+ "type": "passive",+ "description": "Drain of N-channel MOSFET; VDSS 60 V, continuous ID ±115 mAdc (TC=25 °C), pulsed IDM ±800 mAdc, RDS(on) max 7.5 Ω at VGS=5 V/ID=50 mA."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-4-6",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-7",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 6,+ "cost_usd": 0.1544,+ "at": "2026-09-18T05:49:25"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586172828182065152",+ "pages": 6,+ "sha256": "1dc34291b20fbdb9",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 3,+ "described": 3,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}