# L1N4007FT1G

**LRC** · Diodes - General Purpose · SOD-123FL

L1N4007FT1G from LRC, in a SOD-123FL. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K | passive | Cathode: the banded/marked end per the datasheet; pad 1 of the KiCad diode footprint. |
| 2 | A | passive | Anode. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOD-123FL |
| Category | Diodes |
| Pins | 2 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum repetitive peak reverse voltage (1000V column, L1N4007FT1G) | VRRM |  |  | 1000 | V |  | 1 |
| Maximum RMS voltage (1000V column) | VRMS |  |  | 700 | V |  | 1 |
| Maximum DC blocking voltage (1000V column) | VDC |  |  | 1000 | V |  | 1 |
| Maximum average forward rectified current | IF(AV) |  |  | 1 | A | Lead length at TC = 75°C (Note 1: 8.0mm2 land areas) | 1 |
| Peak forward surge current | IFSM |  |  | 30 | A | 8.3ms single half sine-wave superimposed on rated load (JEDEC Method) | 1 |
| Maximum instantaneous forward voltage | VF |  |  | 1.1 | V | at 1.0A | 1 |
| Maximum DC reverse current | IR |  |  | 5 | µA | TJ = 25°C, at rated DC blocking voltage | 1 |
| Maximum DC reverse current | IR |  |  | 50 | µA | TJ = 125°C, at rated DC blocking voltage | 1 |
| Operating junction temperature range | TJ | -55 |  | 150 | °C |  | 1 |
| Storage temperature range | TSTG | -55 |  | 150 | °C |  | 1 |
| Typical thermal resistance | RθJA |  | 110 |  | °C/W | Note 1: 8.0mm2 (.013mm thick) land areas | 1 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts |  | tin | Terminals: Tin Plated, solderable per MIL-STD-750, Method 2026 | 1 |

## CAD (KiCad official)

- Symbol: `L1N4007FT1G`
- Footprint: `Diode_SMD:D_SOD-123F`
- 3D model: SOD-123FL (KiCad packages3D, STEP)
- 3D model files: `l1n4007ft1g-etched.step` / `l1n4007ft1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `l1n4007ft1g.step` / `l1n4007ft1g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LRC datasheet](docs/l1n4007ft1g-datasheet.pdf) (4 pp, sha256 `9a29ca71f1f267bf`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins`, primary `cathode-band convention` (convention), consensus `off` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/l1n4007ft1g-datasheet.pdf)