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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

KTI226V S RKTU

Intel Altera · Ethernet Controllers · VQFN-56-EP(7x7)

KTI226V S RKTU from Intel Altera, in a VQFN-56-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	LAN_PWR_GOOD	input	3.3 Vdc power and clock good indication input; low-to-high transition initializes the I225/I226.
2	LAN_DISABLE_N	input	3.3 Vdc asynchronous input signal for D3Cold support.
3	PE_CLKREQ_N	bidirectional	PCIe Clock Request open-drain signal for power management.
4	ULP_WAKE_N	bidirectional	Ultra Low Power wake open-drain signal used by external Management Controller (CSME) to exit ULP mode.
5	VDD_CTRL	power_out	Internal Switching Voltage Regulator (iSVR) output node; connect to 1.0 µH inductor and capacitors to provide 0.95 Vdc ±10% core power rail.
6	VDD_CTRL	power_out	Internal Switching Voltage Regulator (iSVR) output node; connect to 1.0 µH inductor and capacitors to provide 0.95 Vdc ±10% core power rail.
7	+3.3V_DC	power_in	DC-DC converter input power supply; nominal 3.3 Vdc with ±10% tolerance.
8	RESERVED	power_in	Fusing Domain Supply pin; tie to ground during normal operation.
9	VDD_CORE	power_in	Core-Voltage Domain Supply; nominal 0.95 Vdc with ±10% tolerance.
10	SMB_DATA	bidirectional	SMBus Data open-drain signal; pull up to 3.3 Vdc through 499 Ω resistor for 1 MHz operation.
11	SMB_CLK	bidirectional	SMBus Clock open-drain signal; pull up to 3.3 Vdc through 499 Ω resistor for 1 MHz operation.
12	PE_WAKE_N	bidirectional	PCIe Wake open-drain signal; driven low on wake-up event detection.
13	PE_RST_N	input	PCIe Reset input signal indicating both PCIe power and clock are available.
14	+3.3V_PAD	power_in	Pad-Voltage Domain Supply; nominal 3.3 Vdc with ±10% tolerance at corners.
15	SDP0	bidirectional	Software Defined Pin 0; configurable as input or output mode by firmware.
16	JTAG_RSTN	input	JTAG Test Reset input signal; low state activates JTAG reset and SDPs; internal weak pull-down maintains reset if open.
17	JTAG_TMS_SDP2	bidirectional	JTAG Test Mode Select signal for JTAG communication.
18	JTAG_TDO/MDI_LANE_SWAP	output	JTAG Test Data Output or MDI Lane Swap strapping pin; high for default lanes, low for swapped configuration.
19	JTAG_TDI_SDP1	input	JTAG Test Data Input signal.
20	RBIAS	bidirectional	Analog impedance tuning pad; connect external resistor for PCIe impedance calibration.
21	PE_CLK_P	input	Differential PCIe Clock input (positive); 100 MHz external reference clock for PHY.
22	PE_CLK_N	input	Differential PCIe Clock input (negative); 100 MHz external reference clock for PHY.
23	+3.3V_VPH	power_in	PCIe High-Voltage Domain Supply; nominal 3.3 Vdc with ±10% tolerance.
24	PE_Tx_N	output	Differential PCIe Transmit output (negative); AC-coupled differential 5 Gb/s transmission.
25	PE_Tx_P	output	Differential PCIe Transmit output (positive); AC-coupled differential 5 Gb/s transmission.
26	VDD_VP	power_in	PCIe Low-Voltage Domain Supply; nominal 0.95 Vdc with ±10% tolerance.
27	PE_Rx_N	input	Differential PCIe Receive input (negative); AC-coupled differential 5 Gb/s reception.
28	PE_Rx_P	input	Differential PCIe Receive input (positive); AC-coupled differential 5 Gb/s reception.
29	JTAG_CLK	input	JTAG Test Clock input signal; TDI, TDO, and TMS are synchronous to this clock.
30	LED2	output	Programmable LED output; configurable via LEDCTL register for link status indication.
31	LED1	output	Programmable LED output; configurable via LEDCTL register for link status indication.
32	LED0	output	Programmable LED output; configurable via LEDCTL register for link status indication.
33	+3.3V_PAD	power_in	Pad-Voltage Domain Supply; nominal 3.3 Vdc with ±10% tolerance at corners.
34	SPI_DOUT/SEC_ENA	output	SPI Data Output and Flash Security strapping pin; requires external 10 kΩ pull-up resistor.
35	SPI_CLK	output	SPI Clock output to serial flash; requires external 10 kΩ pull-down resistor.
36	SPI_DIN/AUX_PWR	input	SPI Data Input and AUX_PWR strapping pin; requires external 10 kΩ pull-up for D3cold auxiliary power support.
37	SPI_CS_N/PCIE_ENA	output	SPI Chip Select active-low output and PCIe Enable strapping pin; requires external 10 kΩ pull-up.
38	VDD_CORE	power_in	Core-Voltage Domain Supply; nominal 0.95 Vdc with ±10% tolerance.
39	+3.3V_XO	power_in	Crystal Oscillator Pad-Voltage Domain Supply; nominal 3.3 Vdc with ±10% tolerance.
40	XTAL_OUT	output	Crystal Oscillator output; connect 25 MHz crystal between XTAL_IN and XTAL_OUT with load capacitances to ground.
41	XTAL_IN	input	Crystal Oscillator input; connect 25 MHz crystal between XTAL_IN and XTAL_OUT with load capacitances to ground.
42	PHY_CAL	passive	Calibration network connection for GbE PHY AFE tuning and impedance calibration.
43	+3.3V_CDB	power_in	CDB High-Voltage Domain Supply; nominal 3.3 Vdc with ±10% tolerance.
44	VDD_A	power_in	Low-Voltage Domain Supply; nominal 0.95 Vdc with ±10% tolerance for AFE and CDB mixed-signal blocks.
45	MDI_A_P	bidirectional	Differential Ethernet Media Interface pair A positive leg; AC-coupled analog signal for Ethernet transceiver.
46	MDI_A_N	bidirectional	Differential Ethernet Media Interface pair A negative leg; AC-coupled analog signal for Ethernet transceiver.
47	+3.3V_A	power_in	High-Voltage Domain Supply for AFE; nominal 3.3 Vdc with ±10% tolerance.
48	MDI_B_P	bidirectional	Differential Ethernet Media Interface pair B positive leg; AC-coupled analog signal for Ethernet transceiver.
49	MDI_B_N	bidirectional	Differential Ethernet Media Interface pair B negative leg; AC-coupled analog signal for Ethernet transceiver.
50	VDD_A	power_in	Low-Voltage Domain Supply; nominal 0.95 Vdc with ±10% tolerance for AFE and CDB mixed-signal blocks.
51	MDI_C_P	bidirectional	Differential Ethernet Media Interface pair C positive leg; AC-coupled analog signal for Ethernet transceiver.
52	MDI_C_N	bidirectional	Differential Ethernet Media Interface pair C negative leg; AC-coupled analog signal for Ethernet transceiver.
53	+3.3V_A	power_in	High-Voltage Domain Supply for AFE; nominal 3.3 Vdc with ±10% tolerance.
54	MDI_D_P	bidirectional	Differential Ethernet Media Interface pair D positive leg; AC-coupled analog signal for Ethernet transceiver.
55	MDI_D_N	bidirectional	Differential Ethernet Media Interface pair D negative leg; AC-coupled analog signal for Ethernet transceiver.
56	VDD_A	power_in	Low-Voltage Domain Supply; nominal 0.95 Vdc with ±10% tolerance for AFE and CDB mixed-signal blocks.
57	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Intel Altera
Package	VQFN-56-EP(7x7)
Category	Interface
Pins	57

CAD (KiCad official)

Symbol: KTI226V S RKTU
Footprint: Package_DFN_QFN:QFN-56-1EP_7x7mm_P0.4mm_EP4x4mm
3D model: VQFN-56-EP(7x7) (KiCad packages3D, STEP)

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Intel Altera datasheet (59 pp, sha256 563d3f9a8e853651, retrieved 2026-09-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF