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KSZ9897RTXI-TR

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Microchip Tech Interface - Specialized, TQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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KSZ9897RTXI-TR

Microchip Tech · Interface - Specialized · TQFP-128(14x14)

KSZ9897RTXI-TR from Microchip Tech, in a TQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXRX1P_A passive Port 1 1000BASE-T differential data pair A positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
2 TXRX1M_A passive Port 1 1000BASE-T differential data pair A negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
3 AVDDL power_in +1.2V analog power supply for the PHY core.
4 TXRX1P_B passive Port 1 1000BASE-T differential data pair B positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
5 TXRX1M_B passive Port 1 1000BASE-T differential data pair B negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
6 TXRX1P_C passive Port 1 1000BASE-T differential data pair C positive.
7 TXRX1M_C passive Port 1 1000BASE-T differential data pair C negative.
8 TXRX1P_D passive Port 1 1000BASE-T differential data pair D positive.
9 TXRX1M_D passive Port 1 1000BASE-T differential data pair D negative.
10 AVDDH power_in +2.5V analog power supply for the PHY transceivers and XI/XO clock interface.
11 DVDDL power_in +1.2V digital core power supply.
12 TXRX2P_A passive Port 2 1000BASE-T differential data pair A positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
13 TXRX2M_A passive Port 2 1000BASE-T differential data pair A negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
14 AVDDL power_in +1.2V analog power supply for the PHY core.
15 TXRX2P_B passive Port 2 1000BASE-T differential data pair B positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
16 TXRX2M_B passive Port 2 1000BASE-T differential data pair B negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
17 TXRX2P_C passive Port 2 1000BASE-T differential data pair C positive.
18 TXRX2M_C passive Port 2 1000BASE-T differential data pair C negative.
19 AVDDL power_in +1.2V analog power supply for the PHY core.
20 TXRX2P_D passive Port 2 1000BASE-T differential data pair D positive.
21 TXRX2M_D passive Port 2 1000BASE-T differential data pair D negative.
22 AVDDH power_in +2.5V analog power supply for the PHY transceivers and XI/XO clock interface.
23 DVDDL power_in +1.2V digital core power supply.
24 TXRX3P_A passive Port 3 1000BASE-T differential data pair A positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
25 TXRX3M_A passive Port 3 1000BASE-T differential data pair A negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
26 TXRX3P_B passive Port 3 1000BASE-T differential data pair B positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
27 TXRX3M_B passive Port 3 1000BASE-T differential data pair B negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
28 TXRX3P_C passive Port 3 1000BASE-T differential data pair C positive.
29 TXRX3M_C passive Port 3 1000BASE-T differential data pair C negative.
30 AVDDL power_in +1.2V analog power supply for the PHY core.
31 TXRX3P_D passive Port 3 1000BASE-T differential data pair D positive.
32 TXRX3M_D passive Port 3 1000BASE-T differential data pair D negative.
33 AVDDH power_in +2.5V analog power supply for the PHY transceivers and XI/XO clock interface.
34 TXRX4P_A passive Port 4 1000BASE-T differential data pair A positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
35 TXRX4M_A passive Port 4 1000BASE-T differential data pair A negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
36 AVDDL power_in +1.2V analog power supply for the PHY core.
37 TXRX4P_B passive Port 4 1000BASE-T differential data pair B positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
38 TXRX4M_B passive Port 4 1000BASE-T differential data pair B negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
39 TXRX4P_C passive Port 4 1000BASE-T differential data pair C positive.
40 TXRX4M_C passive Port 4 1000BASE-T differential data pair C negative.
41 AVDDL power_in +1.2V analog power supply for the PHY core.
42 TXRX4P_D passive Port 4 1000BASE-T differential data pair D positive.
43 TXRX4M_D passive Port 4 1000BASE-T differential data pair D negative.
44 AVDDH power_in +2.5V analog power supply for the PHY transceivers and XI/XO clock interface.
45 DVDDL power_in +1.2V digital core power supply.
46 GND power_in Ground connection.
47 GND power_in Ground connection.
48 TX_CLK6/REFCLKI6 bidirectional Port 6 25/2.5MHz MII transmit clock (input in MAC mode) or 50MHz RMII reference clock input, or 125/25/2.5MHz RGMII transmit clock input; powered from VDDIO.
49 TX_EN6/TX_CTL6 input Port 6 transmit enable in MII/RMII modes or transmit control in RGMII mode, with internal pull-down.
50 TX_ER6 input Port 6 MII transmit error input; not used in RMII or RGMII modes and should not be connected in those modes.
51 COL6 bidirectional Port 6 MII collision detect (output in PHY mode, input in MAC mode); not used in RMII or RGMII modes and should not be connected.
52 TXD6_3 input Port 6 MII/RGMII transmit data bus bit 3; not used in RMII mode and should not be connected in that mode.
53 TXD6_2 input Port 6 MII/RGMII transmit data bus bit 2; not used in RMII mode and should not be connected in that mode.
54 TXD6_1 input Port 6 MII/RMII/RGMII transmit data bus bit 1.
55 TXD6_0 input Port 6 MII/RMII/RGMII transmit data bus bit 0.
56 DVDDL power_in +1.2V digital core power supply.
57 RX_CLK6/REFCLKO6 bidirectional Port 6 MII receive clock (output in PHY mode), RMII 50MHz reference clock output in clock mode, or RGMII 125/25/2.5MHz receive clock output.
58 RX_DV6/CRS_DV6/RX_CTL6 output Port 6 MII receive data valid, RMII carrier sense/receive data valid, or RGMII receive control output; also a configuration strap pin.
59 RX_ER6 output Port 6 MII receive error output; not used in RMII or RGMII modes and should not be connected in those modes.
60 CRS6 bidirectional Port 6 MII carrier sense (output in PHY mode, input in MAC mode); not used in RMII or RGMII modes and should not be connected.
61 VDDIO power_in +3.3V, +2.5V or +1.8V I/O power supply for the digital I/Os.
62 RXD6_3 output Port 6 MII/RGMII receive data bus bit 3 and configuration strap pin; not used in RMII mode.
63 RXD6_2 output Port 6 MII/RGMII receive data bus bit 2 and configuration strap pin; not used in RMII mode.
64 RXD6_1 output Port 6 MII/RMII/RGMII receive data bus bit 1 and configuration strap pin.
65 RXD6_0 output Port 6 MII/RMII/RGMII receive data bus bit 0 and configuration strap pin.
66 TX_CLK7/REFCLKI7 bidirectional Port 7 MII transmit clock (input in MAC mode), RMII 50MHz reference clock input, or RGMII 125/25/2.5MHz transmit clock input; powered from VDDIO.
67 TX_EN7/TX_CTL7 input Port 7 transmit enable in MII/RMII modes or transmit control in RGMII mode, with internal pull-down.
68 TX_ER7 input Port 7 MII transmit error input; not used in RMII or RGMII modes and should not be connected in those modes.
69 COL7 bidirectional Port 7 MII collision detect (output in PHY mode, input in MAC mode); not used in RMII or RGMII modes and should not be connected.
70 TXD7_3 input Port 7 MII/RGMII transmit data bus bit 3; not used in RMII mode and should not be connected in that mode.
71 TXD7_2 input Port 7 MII/RGMII transmit data bus bit 2; not used in RMII mode and should not be connected in that mode.
72 TXD7_1 input Port 7 MII/RMII/RGMII transmit data bus bit 1.
73 TXD7_0 input Port 7 MII/RMII/RGMII transmit data bus bit 0.
74 DVDDL power_in +1.2V digital core power supply.
75 RX_CLK7/REFCLKO7 bidirectional Port 7 MII receive clock (output in PHY mode), RMII 50MHz reference clock output in clock mode, or RGMII 125/25/2.5MHz receive clock output.
76 RX_DV7/CRS_DV7/RX_CTL7 output Port 7 MII receive data valid, RMII carrier sense/receive data valid, or RGMII receive control output; also a configuration strap pin.
77 VDDIO power_in +3.3V, +2.5V or +1.8V I/O power supply for the digital I/Os.
78 RX_ER7 output Port 7 MII receive error output; not used in RMII or RGMII modes and should not be connected in those modes.
79 CRS7 bidirectional Port 7 MII carrier sense (output in PHY mode, input in MAC mode); not used in RMII or RGMII modes and should not be connected.
80 RXD7_3 output Port 7 MII/RGMII receive data bus bit 3 and configuration strap pin; not used in RMII mode.
81 RXD7_2 output Port 7 MII/RGMII receive data bus bit 2 and configuration strap pin; not used in RMII mode.
82 RXD7_1 output Port 7 MII/RMII/RGMII receive data bus bit 1 and configuration strap pin.
83 RXD7_0 output Port 7 MII/RMII/RGMII receive data bus bit 0 and configuration strap pin.
84 GND power_in Ground connection.
85 LED4_0 output Port 4 LED indicator 0, active low output that sinks current to light an LED; also a configuration strap pin.
86 LED4_1 output Port 4 LED indicator 1, active low output that sinks current to light an LED; also a configuration strap pin.
87 DVDDL power_in +1.2V digital core power supply.
88 LED3_0 output Port 3 LED indicator 0, active low output that sinks current to light an LED.
89 LED3_1 output Port 3 LED indicator 1, active low output that sinks current to light an LED; also a configuration strap pin.
90 NC unconnected No connect; must be left unconnected for proper operation.
91 LED2_0 output Port 2 LED indicator 0, active low output that sinks current to light an LED; also a configuration strap pin.
92 LED2_1 output Port 2 LED indicator 1, active low output that sinks current to light an LED; also a configuration strap pin.
93 PME_N output Power management event output, active low by default, indicating an energy detect event to wake the system; requires an external pull-up for active-low operation.
94 INTRP_N output Active low open-drain interrupt output that requires an external pull-up resistor; also the NAND tree output.
95 CLKO_25_125 output 25/125MHz reference clock output derived from the crystal input, powered from VDDIO.
96 RESET_N input Active low system reset that must be asserted during or after power-on, with an RC circuit suggested for power-on reset.
97 SDO output SPI data output (MISO); not used in I2C or MIIM modes.
98 SDI/SDA/MDIO bidirectional SPI data input (MOSI), I2C data, or MIIM data in/out; open-drain in output state and requires an external 1.0kΩ to 4.7kΩ pull-up to VDDIO.
99 VDDIO power_in +3.3V, +2.5V or +1.8V I/O power supply for the digital I/Os.
100 SCS_N input SPI chip select, active low; not used in I2C or MIIM modes.
101 SCL/MDC input SPI/I2C serial clock or MIIM management clock (MDC) input to the slave device.
102 LED5_0 output Port 5 LED indicator 0, active low output that sinks current to light an LED.
103 LED5_1 output Port 5 LED indicator 1, active low output that sinks current to light an LED; also a configuration strap pin.
104 DVDDL power_in +1.2V digital core power supply.
105 LED1_0 output Port 1 LED indicator 0, active low output that sinks current to light an LED.
106 LED1_1 output Port 1 LED indicator 1, active low output that sinks current to light an LED; also a configuration strap pin.
107 GND power_in Ground connection.
108 NC unconnected No connect; must be left unconnected for proper operation.
109 GND power_in Ground connection.
110 DVDDL power_in +1.2V digital core power supply.
111 AVDDH power_in +2.5V analog power supply for the PHY transceivers and XI/XO clock interface.
112 TXRX5P_A passive Port 5 1000BASE-T differential data pair A positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
113 TXRX5M_A passive Port 5 1000BASE-T differential data pair A negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
114 AVDDL power_in +1.2V analog power supply for the PHY core.
115 TXRX5P_B passive Port 5 1000BASE-T differential data pair B positive; 100BASE-TX and 10BASE-Te also use the A and B pairs.
116 TXRX5M_B passive Port 5 1000BASE-T differential data pair B negative; 100BASE-TX and 10BASE-Te also use the A and B pairs.
117 TXRX5P_C passive Port 5 1000BASE-T differential data pair C positive.
118 TXRX5M_C passive Port 5 1000BASE-T differential data pair C negative.
119 AVDDL power_in +1.2V analog power supply for the PHY core.
120 TXRX5P_D passive Port 5 1000BASE-T differential data pair D positive.
121 TXRX5M_D passive Port 5 1000BASE-T differential data pair D negative.
122 AVDDH power_in +2.5V analog power supply for the PHY transceivers and XI/XO clock interface.
123 GND power_in Ground connection.
124 AVDDL power_in +1.2V analog power supply for the PHY core.
125 XO output Crystal clock output connected to one crystal lead for 25MHz crystal use; left unconnected when an oscillator drives XI.
126 XI input Crystal clock or oscillator input requiring 25MHz with ±50ppm tolerance.
127 ISET passive Transmit output current set resistor, which must connect to GND through a 6.04kΩ 1% resistor.
128 AVDDH power_in +2.5V analog power supply for the PHY transceivers and XI/XO clock interface.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package TQFP-128(14x14)
Category Communication Interface Chip/UART/485/232
Pins 128

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (AVDDL, DVDDL) -0.5 1.8 V 168
Supply Voltage (AVDDH, VDDIO) -0.5 5 V 168
Input Voltage (all inputs) -0.5 5 V 168
Output Voltage (all outputs) -0.5 5 V 168
Lead Temperature (soldering, 20 sec.) 260 oC soldering, 20 sec. 168
Storage Temperature (TS) TS -65 150 oC 168
Maximum Junction Temperature (TJ) TJ 125 oC 168
HBM ESD Performance -6 6 kV HBM 168
Supply Voltage (AVDDL, DVDDL) 1.14 1.26 V 168
Supply Voltage (AVDDH) 2.375 2.625 V 168
Supply Voltage (VDDIO @ 3.3V) VDDIO 3.135 3.465 V VDDIO @ 3.3V 168
Supply Voltage (VDDIO @ 2.5V) VDDIO 2.375 2.625 V VDDIO @ 2.5V 168
Supply Voltage (VDDIO @ 1.8V) VDDIO 1.71 1.89 V VDDIO @ 1.8V 168
Ambient Operating Temperature in Still Air (TA) TA -40 85 oC Industrial version (Note 6-1) 168
AVDDH supply current IDD_AH 330 mA Full 1000 Mbps; VDDIO @ 3.3V; Ports 1-5 in 1000BASE-T; Ports 6 & 7 in RGMII (1000 Mbps); all ports 100% utilization 169
VDDIO supply current IDD_IO 80 mA Full 1000 Mbps; all ports 100% utilization 169
AVDDL supply current IDD_CA 460 mA Full 1000 Mbps; all ports 100% utilization 169
DVDDL supply current IDD_CD 750 mA Full 1000 Mbps; all ports 100% utilization 169
AVDDH supply current IDD_AH 150 mA Mixed 1000/100 Mbps; VDDIO @ 3.3V; Ports 1-5 in 100BASE-TX; Ports 6 & 7 in RGMII (1000 Mbps); all ports 100% utilization 169
AVDDL supply current IDD_CA 140 mA Mixed 1000/100 Mbps; all ports 100% utilization 169
DVDDL supply current IDD_CD 350 mA Mixed 1000/100 Mbps; all ports 100% utilization 169
AVDDH supply current IDD_AH 140 mA Full 100 Mbps; VDDIO @ 3.3V; Ports 1-5 in 100BASE-TX; Ports 6 & 7 in MII (100 Mbps); all ports 100% utilization 169
VDDIO supply current IDD_IO 35 mA Full 100 Mbps; all ports 100% utilization 169
AVDDH supply current IDD_AH 100 mA Full 10 Mbps; VDDIO @ 3.3V; Ports 1-5 in 10BASE-Te; Ports 6 & 7 in MII (10 Mbps); all ports 100% utilization 169
VDDIO supply current (3.3V) IDD_IO 30 mA Full 10 Mbps; all ports 100% utilization 169
AVDDL supply current IDD_CA 30 mA Full 10 Mbps; all ports 100% utilization 169
DVDDL supply current IDD_CD 150 mA Full 10 Mbps; all ports 100% utilization 169
AVDDH supply current IDD_AH 20 mA Power management - energy detect mode 169
AVDDH supply current IDD_AH 2 mA Power management - global soft power down mode 169
VDDIO supply current (3.3V) IDD_IO 6 mA Power management - global soft power down mode 169
AVDDL supply current IDD_CA 0.01 mA Power management - global soft power down mode 169
DVDDL supply current IDD_CD 5 mA Power management - global soft power down mode 169
Input High Voltage (CMOS input buffer) VIH 2.1 V VDDIO = 3.3V 170
Input High Voltage (CMOS input buffer) VIH 1.7 V VDDIO = 2.5V 170
Input High Voltage (CMOS input buffer) VIH 1.3 V VDDIO = 1.8V 170
Input Low Voltage (CMOS input buffer) VIL 0.9 V VDDIO = 3.3V 170
Input Low Voltage (CMOS input buffer) VIL 0.6 V VDDIO = 1.8V 170
Input Current IIN -10 10 µA VIN = GND ~ VDDIO 170
Output High Voltage (O8 buffer) VOH 2.4 V VDDIO = 3.3V; IOH = 8 mA 170
Output High Voltage (O8 buffer) VOH 1.9 V VDDIO = 2.5V; IOH = 8 mA 170
Output High Voltage (O8 buffer) VOH 1.5 V VDDIO = 1.8V; IOH = 6 mA 170
Output Low Voltage (O8 buffer) VOL 0.4 V VDDIO = 3.3V; IOL = 8 mA 170
Output Low Voltage (O8 buffer) VOL 0.2 V VDDIO = 1.8V; IOL = 6 mA 170
Peak Differential Output (100BASE-TX) VO 0.95 1.05 V 100Ω termination on the differential output 170
Output Voltage Imbalance Vimb 2 % 100Ω termination on the differential output 170
Overshoot 5 % 170
Peak Differential Output Voltage (10BASE-Te) Vp 1.54 1.75 1.96 V 100Ω termination on the differential output 171
Junction to Case Characterization JT 0.04 oC/W 0 m/s air velocity (Note 6-2) 168
Junction to Ambient Resistance JA 11.3 oC/W 6-layer PCB per JESD51 (Note 6-3) 168
Junction to Ambient Resistance JA 14.4 oC/W 4-layer PCB per JESD51 (Note 6-3) 168
Junction to Case Resistance JC 1.5 oC/W 6-layer PCB per JESD51 (Note 6-4) 168
Junction to Case Resistance JC 1.21 oC/W 4-layer PCB per JESD51 (Note 6-4) 168

CAD (KiCad official)

  • Symbol: KSZ9897RTXI-TR
  • Footprint: Package_QFP:TQFP-128_14x14mm_P0.4mm
  • 3D model: TQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: ksz9897rtxi-tr-etched.step / ksz9897rtxi-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz9897rtxi-tr.step / ksz9897rtxi-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (196 pp, sha256 72b89179ed6a42a7, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF