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KSZ9131RNXC-TR

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Microchip Tech Buffer/Driver/Transceiver, QFN-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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KSZ9131RNXC-TR

Microchip Tech · Buffer/Driver/Transceiver · QFN-48(7x7)

KSZ9131RNXC-TR from Microchip Tech, in a QFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDDH power_in +2.5/3.3V analog power supply for the transceiver (Automotive Grade 2 requires +2.5V).
2 TXRXP_A bidirectional Media Dependent Interface pair A positive signal; BI_DA+ in 1000BASE-T and TX+/RX+ in 10/100 MDI/MDI-X modes.
3 TXRXM_A bidirectional Media Dependent Interface pair A negative signal; BI_DA- in 1000BASE-T and TX-/RX- in 10/100 MDI/MDI-X modes.
4 AVDDL power_in +1.2V analog power supply for the transceiver core.
5 TXRXP_B bidirectional Media Dependent Interface pair B positive signal; BI_DB+ in 1000BASE-T and RX+/TX+ in 10/100 modes.
6 TXRXM_B bidirectional Media Dependent Interface pair B negative signal; BI_DB- in 1000BASE-T and RX-/TX- in 10/100 modes.
7 TXRXP_C bidirectional Media Dependent Interface pair C positive signal; BI_DC+ in 1000BASE-T and not used in 10/100 modes.
8 TXRXM_C bidirectional Media Dependent Interface pair C negative signal; BI_DC- in 1000BASE-T and not used in 10/100 modes.
9 AVDDL power_in +1.2V analog power supply for the transceiver core.
10 TXRXP_D bidirectional Media Dependent Interface pair D positive signal; BI_DD+ in 1000BASE-T and not used in 10/100 modes.
11 TXRXM_D bidirectional Media Dependent Interface pair D negative signal; BI_DD- in 1000BASE-T and not used in 10/100 modes.
12 AVDDH power_in +2.5/3.3V analog power supply for the transceiver.
13 NC unconnected No connect; not bonded internally and may be connected to ground for footprint compatibility with older devices.
14 NC unconnected No connect; not bonded internally and may be connected to DVDDL for footprint compatibility with older devices.
15 LED2/PHYAD1 bidirectional Programmable LED2 output (VO8) that doubles as PHY address strap PHYAD1, sampled at power-up/reset (pulled-up = 1, pulled-down = 0).
16 DVDDH power_in +3.3/2.5/1.8V variable I/O digital power supply (Automotive Grade 2 requires +1.8V or +2.5V).
17 LED1/PME_N1/PHYAD0 bidirectional Programmable LED1 output (VO8), also PME_N1 wake-on-LAN output and PHY address strap PHYAD0 sampled at reset.
18 DVDDL power_in +1.2V digital core power supply input.
19 TXD0 input RGMII transmit data bit 0 from the MAC into the PHY (variable voltage input, DVDDH I/O level).
20 TXD1 input RGMII transmit data bit 1 from the MAC into the PHY (variable voltage input, DVDDH I/O level).
21 TXD2 input RGMII transmit data bit 2 from the MAC into the PHY (variable voltage input, DVDDH I/O level).
22 TXD3 input RGMII transmit data bit 3 from the MAC into the PHY (variable voltage input, DVDDH I/O level).
23 DVDDL power_in +1.2V digital core power supply input.
24 TXC input RGMII transmit reference clock from the MAC used to latch TX data; 125 MHz for 1000BASE-T, 25 MHz for 100BASE-TX, 2.5 MHz for 10BASE-T.
25 TX_CTL input RGMII transmit control combining TX enable (TXEN) and transmit error (TXER) per the RGMII specification.
26 DVDDL power_in +1.2V digital core power supply input.
27 RXD3/MODE3 bidirectional RGMII receive data bit 3 to the MAC (VO24), also MODE3 device-mode strap sampled at reset.
28 RXD2/MODE2 bidirectional RGMII receive data bit 2 to the MAC (VO24), also MODE2 device-mode strap sampled at reset.
29 VSS power_in Digital ground for the device.
30 DVDDL power_in +1.2V digital core power supply input.
31 RXD1/MODE1 bidirectional RGMII receive data bit 1 to the MAC (VO24), also MODE1 device-mode strap sampled at reset.
32 RXD0/MODE0 bidirectional RGMII receive data bit 0 to the MAC (VO24), also MODE0 device-mode strap sampled at reset.
33 RX_CTL/CLK125_EN bidirectional RGMII receive control to the MAC (VO24, receive data valid and receive error); also CLK125_EN strap that enables the 125 MHz clock output when pulled up.
34 DVDDH power_in +3.3/2.5/1.8V variable I/O digital power supply.
35 RXC/PHYAD2 bidirectional RGMII receive reference clock to the MAC (VO24; 125/25/2.5 MHz), also PHYAD2 strap sampled at reset.
36 MDC input Management clock input from the MAC for the MDC/MDIO management interface (Schmitt input with internal pull-up).
37 MDIO bidirectional Management data to and from the MAC; requires an external pull-up to DVDDH in the range 1.0 kOhm to 4.7 kOhm; open-drain or push-pull per MDIO Drive register.
38 INT_N/PME_N2/ALLPHYAD bidirectional Programmable active-low PHY interrupt output (VO8), also PME_N2 wake-on-LAN output and ALLPHYAD strap sampled at reset.
39 DVDDL power_in +1.2V digital core power supply input.
40 DVDDH power_in +3.3/2.5/1.8V variable I/O digital power supply.
41 CLK125_NDO/LED_MODE bidirectional 125 MHz reference clock output (VO24) for the MAC or NAND tree output, also LED_MODE strap sampled at reset (pulled-up = Individual-LED, pulled-down = Tri-color-LED).
42 RESET_N input Chip reset, active low (Schmitt input with internal pull-up); configuration straps are latched on its rising edge.
43 LDO_O output On-chip 1.2V LDO controller output that drives the gate of an external P-channel MOSFET for the core; leave unconnected if 1.2V is supplied externally.
44 AVDDL_PLL power_in +1.2V analog PLL power supply.
45 XO output Crystal output for a 25 MHz crystal lead; left unconnected when an external oscillator is used.
46 XI input Crystal input for a 25 MHz crystal or clock source input from an oscillator; crystal or oscillator tolerance should be +/-50 ppm.
47 NC unconnected No connect; not bonded internally and may be connected to AVDDH for footprint compatibility with older devices.
48 ISET passive PHY bias resistor pin; connect to ground through a 6.04 kOhm 1% resistor.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-48(7x7)
Category Logic ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (DVDDL, AVDDL, AVDDL_PLL) VIN -0.5 1.8 V 121
Supply Voltage (AVDDH) VIN -0.5 5 V 121
Supply Voltage (DVDDH) VIN -0.5 5 V 121
Input Voltage (all inputs) -0.5 5 V 121
Output Voltage (all outputs) -0.5 5 V 121
Lead Temperature (soldering, 10s) 260 °C soldering, 10s 121
Storage Temperature TS -55 150 °C 121
HBM ESD Performance -5 5 kV 121
Supply Voltage (DVDDL, AVDDL, AVDDL_PLL) 1.14 1.32 V 121
Supply Voltage (AVDDH @ 3.3V) 3.135 3.63 V @ 3.3V 121
Supply Voltage (AVDDH @ 2.5V) 2.375 2.75 V @ 2.5V 121
Supply Voltage (DVDDH @ 3.3V) 3.135 3.63 V @ 3.3V 121
Supply Voltage (DVDDH @ 2.5V) 2.375 2.75 V @ 2.5V 121
Supply Voltage (DVDDH @ 1.8V) 1.71 1.98 V @ 1.8V 121
Input voltage (all inputs) -0.3 3.63 V 121
Output voltage (all outputs) -0.3 3.63 V 121
Ambient Temperature (TA Commercial: KSZ9131RNXC) TA 0 70 °C Commercial KSZ9131RNXC 121
Maximum Junction Temperature (TJ max.) TJ 125 °C 121
Low Input Level (ICLK type input buffer) VIL 0.5 V 123
High Input Level (ICLK type input buffer) VIH 2 V 123
Input Leakage (ICLK type input buffer) IIH -10 10 µA 123
Low Input Level (VI type input buffer) VIL 0.9 V DVDDH=3.3V 124
High Input Level (VI type input buffer) VIH 2.1 V DVDDH=3.3V 124
Input Leakage (VI type input buffer) IIH -10 10 µA VIN = VSS or DVDDH 124
Low Output Level (VO8 type buffer) VOL 0.4 V IOL = -8/-8/-6 mA 124
High Output Level (VO8 type buffer) VOH 2.4 V IOH = -8/-8/-6 mA 124
Output Tri-State Leakage (VO8 type buffer) IOZ -10 10 µA 124
Low Output Level (VOD8 type buffer) VOL 0.4 V IOL = -8/-8/-6 mA 125
Output Tri-State Leakage (VOD8 type buffer) IOZ -10 10 µA 125
Low Output Level (VO24 type buffer) VOL 0.4 V IOL = -24/-24/-14 mA 125
High Output Level (VO24 type buffer) VOH 2.4 V IOH = 24/-24/-14 mA 125
Output Tri-State Leakage (VO24 type buffer) IOZ -10 10 µA 125
Peak Differential Output Voltage (1000BASE-T) VOP 670 820 mV IEEE 802.3 clause 40.6.1.2.1 125
Signal Scaling (1000BASE-T) VSC 2 % IEEE 802.3 clause 40.6.1.2.1 125
Transmission Distortion (1000BASE-T) 10 mV IEEE 802.3 clause 40.6.1.2.4 125
Peak Differential Output Voltage (100BASE-TX) VOUT 0.95 1.05 V ANSI X3.263 clause 9.1.2.2 126
Signal Amplitude Symmetry (100BASE-TX) VSS 2 % ANSI X3.263 clause 9.1.4 126
Signal Rise and Fall Time (100BASE-TX) TRF 3 5 ns ANSI X3.263 clause 9.1.6 126
Rise and Fall Symmetry (100BASE-TX) TRFS 0.5 ns ANSI X3.263 clause 9.1.6 126
Duty Cycle Distortion (100BASE-TX) DCD -0.25 0.25 ns ANSI X3.263 clause 9.1.8 126
Overshoot and Undershoot (100BASE-TX) VOS 5 % ANSI X3.263 clause 9.1.3 126
Output Jitter (100BASE-TX) 1.4 ns ANSI X3.263 clause 9.1.9 126
Transmitter Peak Differential Output Voltage (10BASE-T) VOUT 2.2 2.5 2.8 V IEEE 802.3 clause 14.3.1.2.1 126
Output Jitter (10BASE-T) 3.5 ns IEEE 802.3 clause 14.3.1.2.3 126
Output drive range for LDO_O to gate input of P-channel MOSFET (AVDDH=3.3V) VLDO_O 1.2 3.11 V AVDDH = 3.3V for MOSFET source voltage 127
Output drive range for LDO_O to gate input of P-channel MOSFET (AVDDH=2.5V) VLDO_O 1.2 2 V AVDDH = 2.5V for MOSFET source voltage 127
Output of P-channel MOSFET 1.23 1.25 1.32 V 127
MDC period tclkp 120 400 ns 134
MDC high time tclkh 40 ns 134
MDC low time tclkl 40 ns 134
MDIO (read from PHY) output valid from rising edge of MDC tval 80 ns 134
MDIO (write to PHY) input setup time to rising edge of MDC tsu 8 ns 134
MDIO (write to PHY) input hold time after rising edge of MDC tihold 8 ns 134
Frequency Tolerance @ 25oC Ftol -50 50 PPM Note 6-26 135
Frequency Stability Over Temp Ftemp -50 50 PPM Note 6-26 135
Load Capacitance CL 25 pF 135
Equivalent Series Resistance R1 50 Ohm 135
Junction-to-Ambient JA 31 °C/W 0 Meters/second 122
Junction-to-Ambient JA 24 °C/W 2.5 Meters/second 122
Maximum Power Dissipation PMAX 663 mW 1000BASE-T Traffic, 3.3V I/O 122

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs slicer error for 1000BASE-T is +/-32. The largest instantaneous slicer error for 100BASE-TX is +/-64. A higher absolute 45

CAD (KiCad official)

  • Symbol: KSZ9131RNXC-TR
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ksz9131rnxc-tr-etched.step / ksz9131rnxc-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz9131rnxc-tr.step / ksz9131rnxc-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (149 pp, sha256 162ab5b03c292354, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF