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KSZ9031RNXIC

Microchip Tech · Ethernet Transceivers · QFN-48-EP(7x7)

KSZ9031RNXIC from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDDH	power_in	3.3V or 2.5V analog VDD for the transceiver, commercial temperature only.
2	TXRXP_A	bidirectional	Media Dependent Interface[0] positive differential signal; BI_DA+ in 1000BASE-T MDI mode, TX+ or RX+ in 10/100 mode depending on MDI/MDI-X.
3	TXRXM_A	bidirectional	Media Dependent Interface[0] negative differential signal; BI_DA- in 1000BASE-T MDI mode, TX- or RX- in 10/100 mode depending on MDI/MDI-X.
4	AVDDL	power_in	1.2V analog VDD for the core.
5	TXRXP_B	bidirectional	Media Dependent Interface[1] positive differential signal; BI_DB+ in 1000BASE-T MDI mode, RX+ or TX+ in 10/100 mode depending on MDI/MDI-X.
6	TXRXM_B	bidirectional	Media Dependent Interface[1] negative differential signal; BI_DB- in 1000BASE-T MDI mode, RX- or TX- in 10/100 mode depending on MDI/MDI-X.
7	TXRXP_C	bidirectional	Media Dependent Interface[2] positive differential signal; BI_DC+ in 1000BASE-T MDI mode and not used in 10BASE-T/100BASE-TX mode.
8	TXRXM_C	bidirectional	Media Dependent Interface[2] negative differential signal; BI_DC- in 1000BASE-T MDI mode and not used in 10BASE-T/100BASE-TX mode.
9	AVDDL	power_in	1.2V analog VDD for the core.
10	TXRXP_D	bidirectional	Media Dependent Interface[3] positive differential signal; BI_DD+ in 1000BASE-T MDI mode and not used in 10BASE-T/100BASE-TX mode.
11	TXRXM_D	bidirectional	Media Dependent Interface[3] negative differential signal; BI_DD- in 1000BASE-T MDI mode and not used in 10BASE-T/100BASE-TX mode.
12	AVDDH	power_in	3.3V or 2.5V analog VDD for the transceiver, commercial temperature only.
13	NC	unconnected	Not bonded; may be connected to digital ground for footprint compatibility with the KSZ9021RN.
14	DVDDL	power_in	1.2V digital VDD for the core.
15	LED2/PHYAD1	bidirectional	Programmable LED2 output; its pull-up or pull-down is latched as PHYAD[1] during power-up/reset.
16	DVDDH	power_in	3.3V, 2.5V, or 1.8V digital VDD for I/O.
17	LED1/PHYAD0/PME_N1	bidirectional	Programmable LED1 output; voltage is sampled at power-up/reset as PHYAD[0], and as PME_N1 output it requires an external pull-up to DVDDH of 1.0 kΩ to 4.7 kΩ and is not open-drain in all modes.
18	DVDDL	power_in	1.2V digital VDD for the core.
19	TXD0	input	RGMII TD0 transmit data input from the MAC.
20	TXD1	input	RGMII TD1 transmit data input from the MAC.
21	TXD2	input	RGMII TD2 transmit data input from the MAC.
22	TXD3	input	RGMII TD3 transmit data input from the MAC.
23	DVDDL	power_in	1.2V digital VDD for the core.
24	GTX_CLK	input	RGMII TXC transmit reference clock input from the MAC.
25	TX_EN	input	RGMII TX_CTL transmit control input from the MAC.
26	DVDDL	power_in	1.2V digital VDD for the core.
27	RXD3/MODE3	bidirectional	RGMII RD3 receive data output; its pull-up or pull-down is latched as MODE3 during power-up/reset.
28	RXD2/MODE2	bidirectional	RGMII RD2 receive data output; its pull-up or pull-down is latched as MODE2 during power-up/reset.
29	VSS	power_in	Digital ground.
30	DVDDL	power_in	1.2V digital VDD for the core.
31	RXD1/MODE1	bidirectional	RGMII RD1 receive data output; its pull-up or pull-down is latched as MODE1 during power-up/reset.
32	RXD0/MODE0	bidirectional	RGMII RD0 receive data output; its pull-up or pull-down is latched as MODE0 during power-up/reset.
33	RX_DV/CLK125_EN	bidirectional	RGMII RX_CTL receive control output; latched as CLK125_EN during power-up/reset to enable the 125 MHz clock output when pulled up.
34	DVDDH	power_in	3.3V, 2.5V, or 1.8V digital VDD for I/O.
35	RX_CLK/PHYAD2	bidirectional	RGMII RXC receive reference clock output; its pull-up or pull-down is latched as PHYAD[2] during power-up/reset.
36	MDC	input	Management data clock input and reference clock for MDIO; has an internal pull-up.
37	MDIO	bidirectional	Management data input/output synchronous to MDC; requires an external pull-up to DVDDH of 1.0 kΩ to 4.7 kΩ.
38	INT_N/PME_N2	output	Programmable interrupt output, active low by default (active high selectable via Register 1Fh bit 14), or PME_N2 wake-up output; requires an external pull-up to DVDDH of 1.0 kΩ to 4.7 kΩ and is not open-drain in all modes.
39	DVDDL	power_in	1.2V digital VDD for the core.
40	DVDDH	power_in	3.3V, 2.5V, or 1.8V digital VDD for I/O.
41	CLK125_NDO/LED_MODE	bidirectional	125 MHz reference clock output for the MAC; its pull-up or pull-down is latched as LED_MODE during power-up/reset (pull-up selects single-LED mode, pull-down tri-color dual-LED mode).
42	RESET_N	input	Active-low chip reset with internal pull-up; hardware strap-ins are latched on its rising edge.
43	LDO_O	output	On-chip 1.2V LDO controller output driving the gate of an external P-channel MOSFET; it must never be driven externally and may be left floating if 1.2V is supplied by the system.
44	AVDDL_PLL	power_in	1.2V analog VDD for the PLL.
45	XO	output	25 MHz crystal feedback; a no connect when an oscillator or external clock source is used.
46	XI	input	Crystal, oscillator, or external clock input at 25 MHz ±50 ppm tolerance.
47	NC	unconnected	Not bonded; may be connected to AVDDH power for footprint compatibility with the KSZ9021RN.
48	ISET	bidirectional	Sets the transmit output level; connect a 12.1 kΩ 1% resistor to ground on this pin.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-48-EP(7x7)
Category	Interface
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage DVDDL, AVDDL, AVDDL_PLL (absolute maximum)	VIN	-0.5		1.8	V		52
Supply voltage AVDDH (absolute maximum)	VIN	-0.5		5	V		52
Supply voltage DVDDH (absolute maximum)	VIN	-0.5		5	V		52
Input voltage (all inputs)		-0.5		5	V		52
Output voltage (all outputs)		-0.5		5	V		52
Lead temperature (soldering)				260	°C	soldering, 10 s	52
Storage temperature	TS	-55		150	°C		52
Supply voltage DVDDL, AVDDL, AVDDL_PLL (operating)	VIN	1.14		1.38	V	1.2V core supply	52
Supply voltage AVDDH @ 3.3V (operating)	VIN	3.135		3.465	V	AVDDH @ 3.3V	52
Supply voltage DVDDH @ 3.3V (operating)	VIN	3.135		3.465	V	DVDDH @ 3.3V	52
Supply voltage DVDDH @ 2.5V (operating)	VIN	2.375		2.625	V	DVDDH @ 2.5V	52
Supply voltage DVDDH @ 1.8V (operating)	VIN	1.71		1.89	V	DVDDH @ 1.8V	52
Ambient temperature (TA Industrial: KSZ9031RNXI)	TA	-40		85	°C	Industrial grade	52
MDIO external pull-up resistor to DVDDH		1		4.7	kΩ	Pin 37 MDIO, pull-up to DVDDH	10
INT_N/PME_N external pull-up resistor to DVDDH		1		4.7	kΩ	Pin 38, interrupt (active low) and PME functions, pull-up to DVDDH	10
Reference clock frequency (XI)			25		MHz	25 MHz crystal or external clock at XI	66
Reference clock frequency tolerance (XI)		-50		50	ppm	25 MHz reference, printed ±50 ppm	66
XI clock input swing (direct coupled, minimum)	VPP	2.5			V	Peak-to-peak swing reference to ground, external clock	66
XI clock input swing (series capacitive coupled, minimum)	VPP	1.5			V	With series capacitive coupling	66
XI clock input swing (maximum)	VPP			3.3	V	Maximum VPP swing is 3.3V +5% per datasheet text	66
Reference clock total period jitter				100	ps	Total period jitter, peak-to-peak, 25 MHz reference	66
Maximum junction temperature	TJ			125	°C	TJ max.	52
Thermal resistance junction-to-ambient	ΘJA		36.34		°C/W		52
Thermal resistance junction-to-case	ΘJC		9.47		°C/W		52

CAD (KiCad official)

Symbol: KSZ9031RNXIC
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
3D model files: ksz9031rnxic-etched.step / ksz9031rnxic-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz9031rnxic.step / ksz9031rnxic.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (79 pp, sha256 5c4f83b0bd94536f, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF