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KSZ9031RNXCC

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Microchip Tech Ethernet ICs, QFN-48-EP(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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KSZ9031RNXCC

Microchip Tech · Ethernet ICs · QFN-48-EP(7x7)

KSZ9031RNXCC from Microchip Tech, in a QFN-48-EP(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDDH power_in Analog VDD for the transceiver at 3.3V or 2.5V, commercial temperature only.
2 TXRXP_A bidirectional Media Dependent Interface pair 0 positive signal, carrying BI_DA+ in 1000BASE-T MDI mode and TX+ or RX+ in 10/100 mode.
3 TXRXM_A bidirectional Media Dependent Interface pair 0 negative signal, carrying BI_DA- in 1000BASE-T MDI mode and TX- or RX- in 10/100 mode.
4 AVDDL power_in Analog VDD of 1.2V for the transceiver core.
5 TXRXP_B bidirectional Media Dependent Interface pair 1 positive signal, carrying BI_DB+ in 1000BASE-T MDI mode and RX+ or TX+ in 10/100 mode.
6 TXRXM_B bidirectional Media Dependent Interface pair 1 negative signal, carrying BI_DB- in 1000BASE-T MDI mode and RX- or TX- in 10/100 mode.
7 TXRXP_C bidirectional Media Dependent Interface pair 2 positive signal, carrying BI_DC+ in 1000BASE-T MDI mode and not used in 10/100 mode.
8 TXRXM_C bidirectional Media Dependent Interface pair 2 negative signal, carrying BI_DC- in 1000BASE-T MDI mode and not used in 10/100 mode.
9 AVDDL power_in Analog VDD of 1.2V for the transceiver core.
10 TXRXP_D bidirectional Media Dependent Interface pair 3 positive signal, carrying BI_DD+ in 1000BASE-T MDI mode and not used in 10/100 mode.
11 TXRXM_D bidirectional Media Dependent Interface pair 3 negative signal, carrying BI_DD- in 1000BASE-T MDI mode and not used in 10/100 mode.
12 AVDDH power_in Analog VDD for the transceiver at 3.3V or 2.5V, commercial temperature only.
13 NC unconnected Not bonded; may be connected to digital ground for footprint compatibility with the KSZ9021RN.
14 DVDDL power_in Digital VDD of 1.2V for the core.
15 LED2/PHYAD1 bidirectional Programmable LED2 output, with the pull-up or pull-down value latched as PHYAD[1] at power-up or reset.
16 DVDDH power_in Digital VDD I/O at 3.3V, 2.5V, or 1.8V.
17 LED1/PHYAD0/PME_N1 bidirectional Programmable LED1 output, with the voltage latched as PHYAD[0] at power-up or reset; PME_N output needs an external pull-up to DVDDH of 1.0 kΩ to 4.7 kΩ.
18 DVDDL power_in Digital VDD of 1.2V for the core.
19 TXD0 input RGMII transmit data bit 0 input (TD0).
20 TXD1 input RGMII transmit data bit 1 input (TD1).
21 TXD2 input RGMII transmit data bit 2 input (TD2).
22 TXD3 input RGMII transmit data bit 3 input (TD3).
23 DVDDL power_in Digital VDD of 1.2V for the core.
24 GTX_CLK input RGMII transmit reference clock input (TXC).
25 TX_EN input RGMII transmit control input (TX_CTL).
26 DVDDL power_in Digital VDD of 1.2V for the core.
27 RXD3/MODE3 bidirectional RGMII receive data bit 3 output (RD3); the pull-up or pull-down value is latched as MODE3 at power-up or reset.
28 RXD2/MODE2 bidirectional RGMII receive data bit 2 output (RD2); the pull-up or pull-down value is latched as MODE2 at power-up or reset.
29 VSS power_in Digital ground.
30 DVDDL power_in Digital VDD of 1.2V for the core.
31 RXD1/MODE1 bidirectional RGMII receive data bit 1 output (RD1); the pull-up or pull-down value is latched as MODE1 at power-up or reset.
32 RXD0/MODE0 bidirectional RGMII receive data bit 0 output (RD0); the pull-up or pull-down value is latched as MODE0 at power-up or reset.
33 RX_DV/CLK125_EN bidirectional RGMII receive control output (RX_CTL); latched as CLK125_NDO output enable at power-up or reset.
34 DVDDH power_in Digital VDD I/O at 3.3V, 2.5V, or 1.8V.
35 RX_CLK/PHYAD2 bidirectional RGMII receive reference clock output (RXC); the pull-up or pull-down value is latched as PHYAD[2] at power-up or reset.
36 MDC input Management data clock input, the reference clock for MDIO (Pin 37), with internal pull-up.
37 MDIO bidirectional Management data input and output, synchronous to MDC, requiring an external pull-up to DVDDH of 1.0 kΩ to 4.7 kΩ.
38 INT_N/PME_N2 output Programmable interrupt output, active low by default; PME_N option requires an external pull-up to DVDDH of 1.0 kΩ to 4.7 kΩ.
39 DVDDL power_in Digital VDD of 1.2V for the core.
40 DVDDH power_in Digital VDD I/O at 3.3V, 2.5V, or 1.8V.
41 CLK125_NDO/LED_MODE bidirectional 125 MHz reference clock output for the MAC; the pull-up or pull-down value is latched as LED_MODE at power-up or reset.
42 RESET_N input Chip reset, active low, with internal pull-up; hardware strap-ins are latched on the rising edge of RESET_N.
43 LDO_O output On-chip 1.2V LDO controller output that drives the gate of a P-channel MOSFET; this pin should never be driven externally.
44 AVDDL_PLL power_in Analog VDD of 1.2V for the PLL.
45 XO output 25 MHz crystal feedback; a no connect if an oscillator or external clock source is used.
46 XI input Crystal, oscillator, or external clock input at 25 MHz with ±50 ppm tolerance.
47 NC unconnected Not bonded; may be connected to AVDDH power for footprint compatibility with the KSZ9021RN.
48 ISET bidirectional Sets the transmit output level; connect a 12.1 kΩ 1% resistor to ground on this pin.
49 P_GND passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-48-EP(7x7)
Category Communication Interface Chip/UART/485/232
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage DVDDL, AVDDL, AVDDL_PLL absolute maximum VIN -0.5 1.8 V DVDDL, AVDDL, AVDDL_PLL 52
Supply voltage AVDDH absolute maximum VIN -0.5 5 V AVDDH 52
Supply voltage DVDDH absolute maximum VIN -0.5 5 V DVDDH 52
Input voltage absolute maximum -0.5 5 V all inputs 52
Output voltage absolute maximum -0.5 5 V all outputs 52
Storage temperature TS -55 150 °C 52
Lead temperature soldering 260 °C soldering, 10s 52
Supply voltage DVDDL, AVDDL, AVDDL_PLL operating VIN 1.14 1.38 V DVDDL, AVDDL, AVDDL_PLL 52
Supply voltage AVDDH @ 3.3V operating VIN 3.135 3.465 V AVDDH @ 3.3V 52
Supply voltage AVDDH @ 2.5V operating VIN 2.375 2.625 V AVDDH @ 2.5V; Commercial temp. only 52
Supply voltage DVDDH @ 3.3V operating VIN 3.135 3.465 V DVDDH @ 3.3V 52
Supply voltage DVDDH @ 2.5V operating VIN 2.375 2.625 V DVDDH @ 2.5V 52
Supply voltage DVDDH @ 1.8V operating VIN 1.71 1.89 V DVDDH @ 1.8V 52
Ambient temperature commercial TA 0 70 °C TA Commercial: KSZ9031RNXC 52
Maximum junction temperature TJ 125 °C TJ max. 52
Thermal resistance junction-to-ambient ΘJA 36.34 °C/W 52
Thermal resistance junction-to-case ΘJC 9.47 °C/W 52

CAD (KiCad official)

  • Symbol: KSZ9031RNXCC
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: QFN-48-EP(7x7) (KiCad packages3D, STEP)
  • 3D model files: ksz9031rnxcc-etched.step / ksz9031rnxcc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz9031rnxcc.step / ksz9031rnxcc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (79 pp, sha256 f7c402264e7b9b65, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF