KSZ9021RL from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	TXRXP_A	bidirectional	Media Dependent Interface[0] positive differential signal, used as TX+ or RX+ in 10/100 modes (MDI or MDI-X) and as BI_DA+ or BI_DB+ in 1000Base-T mode.
2	TXRXM_A	bidirectional	Media Dependent Interface[0] negative differential signal, used as TX- or RX- in 10/100 modes (MDI or MDI-X) and as BI_DA- or BI_DB- in 1000Base-T mode.
3	AGNDH	power_in	Analog ground.
4	AVDDL	power_in	1.2V analog VDD.
5	AVDDL	power_in	1.2V analog VDD.
6	AVDDH	power_in	3.3V analog VDD.
7	TXRXP_B	bidirectional	Media Dependent Interface[1] positive differential signal, used as RX+ or TX+ in 10/100 modes (MDI or MDI-X) and as BI_DB+ or BI_DA+ in 1000Base-T mode.
8	TXRXM_B	bidirectional	Media Dependent Interface[1] negative differential signal, used as RX- or TX- in 10/100 modes (MDI or MDI-X) and as BI_DB- or BI_DA- in 1000Base-T mode.
9	AGNDH	power_in	Analog ground.
10	TXRXP_C	bidirectional	Media Dependent Interface[2] positive differential signal, used in 1000Base-T mode (BI_DC+ or BI_DD+); not used in 10/100 modes.
11	TXRXM_C	bidirectional	Media Dependent Interface[2] negative differential signal, used in 1000Base-T mode (BI_DC- or BI_DD-); not used in 10/100 modes.
12	AVDDL	power_in	1.2V analog VDD.
13	AVDDL	power_in	1.2V analog VDD.
14	TXRXP_D	bidirectional	Media Dependent Interface[3] positive differential signal, used in 1000Base-T mode (BI_DD+ or BI_DC+); not used in 10/100 modes.
15	TXRXM_D	bidirectional	Media Dependent Interface[3] negative differential signal, used in 1000Base-T mode (BI_DD- or BI_DC-); not used in 10/100 modes.
16	AVDDH	power_in	3.3V analog VDD.
17	VSS	power_in	Digital ground.
18	VSS	power_in	Digital ground.
19	LED2 / PHYAD1	bidirectional	Programmable LED2 output (function set by LED_MODE strap on pin 55); its pull-up/pull-down is latched as PHYAD[1] at power-up/reset.
20	DVDDH	power_in	3.3V/2.5V digital VDD.
21	LED1 / PHYAD0	bidirectional	Programmable LED1 output (function set by LED_MODE strap on pin 55); its pull-up/pull-down is latched as PHYAD[0] at power-up/reset.
22	DVDDL	power_in	1.2V digital VDD.
23	VSS	power_in	Digital ground.
24	TXD0	input	RGMII TD0 transmit data bit 0 input from the MAC.
25	TXD1	input	RGMII TD1 transmit data bit 1 input from the MAC.
26	TXD2	input	RGMII TD2 transmit data bit 2 input from the MAC.
27	TXD3	input	RGMII TD3 transmit data bit 3 input from the MAC.
28	VSS	power_in	Digital ground.
29	DVDDL	power_in	1.2V digital VDD.
30	DVDDH	power_in	3.3V/2.5V digital VDD.
31	TX_ER	input	Not used in RGMII mode; the datasheet says to leave this pin as a no connect.
32	GTX_CLK	input	RGMII TXC transmit reference clock input from the MAC (125MHz for 1000Mbps, 25MHz for 100Mbps, 2.5MHz for 10Mbps).
33	TX_EN	input	RGMII TX_CTL transmit control input from the MAC.
34	VSS	power_in	Digital ground.
35	DVDDL	power_in	1.2V digital VDD.
36	RXD3 / MODE3	bidirectional	RGMII RD3 receive data bit 3 output; its pull-up/pull-down is latched as MODE3 strap at power-up/reset.
37	DVDDH	power_in	3.3V/2.5V digital VDD.
38	RXD2 / MODE2	bidirectional	RGMII RD2 receive data bit 2 output; its pull-up/pull-down is latched as MODE2 strap at power-up/reset.
39	VSS	power_in	Digital ground.
40	DVDDL	power_in	1.2V digital VDD.
41	RXD1 / MODE1	bidirectional	RGMII RD1 receive data bit 1 output; its pull-up/pull-down is latched as MODE1 strap at power-up/reset.
42	RXD0 / MODE0	bidirectional	RGMII RD0 receive data bit 0 output; its pull-up/pull-down is latched as MODE0 strap at power-up/reset.
43	RX_DV / CLK125_EN	bidirectional	RGMII RX_CTL receive control output; latched as CLK125_NDO output enable at power-up/reset (pull-up enables, pull-down disables the 125MHz clock).
44	DVDDH	power_in	3.3V/2.5V digital VDD.
45	RX_ER	output	Not used in RGMII mode; the datasheet says to leave this pin as a no connect.
46	RX_CLK / PHYAD2	bidirectional	RGMII RXC receive reference clock output (125MHz, 25MHz or 2.5MHz); its pull-up/pull-down is latched as PHYAD[2] at power-up/reset.
47	CRS	output	Not used in RGMII mode; the datasheet says to leave this pin as a no connect.
48	MDC	input	Management Data Clock input, the reference clock for MDIO (pin 49); input has internal pull-up.
49	MDIO	bidirectional	Management Data Input/Output, synchronous to MDC (pin 48); requires an external pull-up of 1.0k to 4.7k to 3.3V/2.5V digital VDD.
50	COL	output	Not used in RGMII mode; the datasheet says to leave this pin as a no connect.
51	INT_N	output	Programmable interrupt output, active low by default (register 1Fh bit 14 selects active high); requires an external pull-up of 1.0k to 4.7k to 3.3V/2.5V digital VDD.
52	DVDDL	power_in	1.2V digital VDD.
53	VSS	power_in	Digital ground.
54	DVDDL	power_in	1.2V digital VDD.
55	CLK125_NDO / LED_MODE	bidirectional	125MHz reference clock output for the MAC; its pull-up/pull-down is latched as LED_MODE at power-up/reset (pull-up = single LED mode, pull-down = tri-color dual LED mode).
56	RESET_N	input	Active-low chip reset; hardware strap configurations are latched on the rising edge (de-assertion) of RESET_N; input has internal pull-up.
57	LDO_O	output	On-chip 1.2V LDO controller output that drives the gate of an external P-channel MOSFET for the core; can be left floating if 1.2V is supplied by the system.
58	AVDDL_PLL	power_in	1.2V analog VDD for the PLL.
59	XO	output	25MHz crystal feedback; a no connect if an oscillator or external clock source is used.
60	XI	input	Crystal, oscillator or external clock input, 25MHz ±50ppm tolerance.
61	AVDDH	power_in	3.3V analog VDD.
62	ISET	bidirectional	Sets the transmit output level; connect a 4.99K 1% resistor to ground on this pin.
63	AGNDH_BG	power_in	Analog ground for the bandgap reference.
64	AVDDH	power_in	3.3V analog VDD.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	LQFP-64(10x10)
Category	Logic ICs
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (DVDDL, AVDDL, AVDDL_PLL)	DVDDL, AVDDL, AVDDL_PLL	1.14		1.26	V		50
Supply Voltage (AVDDH)	AVDDH	3.135		3.465	V		50
Supply Voltage (DVDDH @ 3.3V)	DVDDH	3.135		3.465	V		50
Supply Voltage (DVDDH @ 2.5V)	DVDDH	2.375		2.625	V		50
Ambient Temperature (TA Commercial: KSZ9021RL/RN)	TA	0		70	°C		50
Supply Voltage (DVDDL, AVDDL, AVDDL_PLL)	DVDDL, AVDDL, AVDDL_PLL	-0.5		1.8	V		50
Supply Voltage (AVDDH)	AVDDH	-0.5		5	V		50
Supply Voltage (DVDDH)	DVDDH	-0.5		5	V		50
Input Voltage (all inputs)		-0.5		5	V		50
Output Voltage (all outputs)		-0.5		5	V		50
Storage Temperature (Ts)	Ts	-55		150	°C		50
Input High Voltage (TTL Inputs)	VIH	2			V		51
Input Low Voltage (TTL Inputs)	VIL			0.8	V		51
Input Current (TTL Inputs)	IIN	-10		10	µA	VIN = GND ~ VDDIO	51
Output High Voltage (TTL Outputs)	VOH	2.4			V	IOH = -4mA	51
Output Low Voltage (TTL Outputs)	VOL			0.4	V	IOL = 4mA	51
Output Tri-State Leakage	/Ioz/			10	µA		52
Peak Differential Output Voltage (100Base-TX)	VO	0.95		1.05	V	100 termination across differential output	52
Output Voltage Imbalance (100Base-TX)	VIMB			2	%	100 termination across differential output	52
Rise/Fall Time (100Base-TX)	tr, tf	3		5	ns		52
Rise/Fall Time Imbalance (100Base-TX)		0		0.5	ns		52
Duty Cycle Distortion (100Base-TX)		-0.25		0.25	ns		52
Overshoot (100Base-TX)				5	%		52
Peak Differential Output Voltage (10Base-T)	VP	2.2		2.8	V	100 termination across differential output	52
Jitter Added Peak-to-peak (10Base-T)				3.5	ns		52
Harmonic Rejection (10Base-T)				-31	dB	Transmit all-one signal sequence	52
Squelch Threshold (10Base-T Receive)	VSQ	300		400	mV	5MHz square wave	52
RGMII Data to Clock Output Skew (at Transmitter)	TskewT	-500		500	ps		53
RGMII Data to Clock Input Skew (at Receiver)	TskewR	1		2.6	ns		53
Clock Cycle Duration for 1000Base-T	Tcyc (1000Base-T)	7.2	8	8.8	ns		53
Clock Cycle Duration for 100Base-TX	Tcyc (100Base-TX)	36	40	44	ns		53
Clock Cycle Duration for 10Base-T	Tcyc (10Base-T)	360	400	440	ns		53

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
housing	abs		• Priority 6: 10Base-T, half-duplex This is known as parallel detection, and allows the KSZ9021RL/RN to establish a link by listening for a fixed signal protocol in the absence of auto-negotiation ad	27

CAD (KiCad official)

Symbol: KSZ9021RL
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ksz9021rl-etched.step / ksz9021rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz9021rl.step / ksz9021rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (67 pp, sha256 6361a105df1c9bc1, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

KSZ9021RL

Verified KSZ9021RL

Verification log 1 record

3D Model

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