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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

KSZ9021GN

Microchip Tech · Ethernet Transceivers · QFN-64-EP(8x8)

KSZ9021GN from Microchip Tech, in a QFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDDH	power_in	3.3V analog VDD.
2	TXRXP_A	bidirectional	Media Dependent Interface[0], positive signal of differential pair; BI_DA+ (MDI) or BI_DB+ (MDI-X) in 1000Base-T, TX+/RX+ in 10/100.
3	TXRXM_A	bidirectional	Media Dependent Interface[0], negative signal of differential pair; BI_DA- (MDI) or BI_DB- (MDI-X) in 1000Base-T, TX-/RX- in 10/100.
4	AVDDL	power_in	1.2V analog VDD.
5	AVDDL	power_in	1.2V analog VDD.
6	NC	unconnected	No connect.
7	TXRXP_B	bidirectional	Media Dependent Interface[1], positive signal of differential pair; BI_DB+ (MDI) or BI_DA+ (MDI-X) in 1000Base-T, RX+/TX+ in 10/100.
8	TXRXM_B	bidirectional	Media Dependent Interface[1], negative signal of differential pair; BI_DB- (MDI) or BI_DA- (MDI-X) in 1000Base-T, RX-/TX- in 10/100.
9	AGNDH	power_in	Analog ground.
10	TXRXP_C	bidirectional	Media Dependent Interface[2], positive signal of differential pair; BI_DC+ (MDI) or BI_DD+ (MDI-X) in 1000Base-T, not used in 10/100.
11	TXRXM_C	bidirectional	Media Dependent Interface[2], negative signal of differential pair; BI_DC- (MDI) or BI_DD- (MDI-X) in 1000Base-T, not used in 10/100.
12	AVDDL	power_in	1.2V analog VDD.
13	AVDDL	power_in	1.2V analog VDD.
14	TXRXP_D	bidirectional	Media Dependent Interface[3], positive signal of differential pair; BI_DD+ (MDI) or BI_DC+ (MDI-X) in 1000Base-T, not used in 10/100.
15	TXRXM_D	bidirectional	Media Dependent Interface[3], negative signal of differential pair; BI_DD- (MDI) or BI_DC- (MDI-X) in 1000Base-T, not used in 10/100.
16	AVDDH	power_in	3.3V analog VDD.
17	LED2/PHYAD1	bidirectional	Programmable LED2 output, and PHYAD[1] strap latched during power-up/reset.
18	DVDDH	power_in	3.3V or 2.5V digital VDD.
19	LED1/PHYAD0	bidirectional	Programmable LED1 output, and PHYAD[0] strap latched during power-up/reset.
20	DVDDL	power_in	1.2V digital VDD.
21	TXD0	input	GMII/MII transmit data 0 input.
22	TXD1	input	GMII/MII transmit data 1 input.
23	TXD2	input	GMII/MII transmit data 2 input.
24	TXD3	input	GMII/MII transmit data 3 input.
25	DVDDL	power_in	1.2V digital VDD.
26	TXD4	input	GMII transmit data 4 input; not used in MII mode and can be driven high or low.
27	TXD5	input	GMII transmit data 5 input; not used in MII mode and can be driven high or low.
28	TXD6	input	GMII transmit data 6 input; not used in MII mode and can be driven high or low.
29	TXD7	input	GMII transmit data 7 input; not used in MII mode and can be driven high or low.
30	DVDDH	power_in	3.3V or 2.5V digital VDD.
31	TX_ER	input	GMII/MII transmit error input; tie low if the MAC does not provide TX_ER.
32	GTX_CLK	input	GMII transmit reference clock input (125MHz for 1000Mbps), sourced by the MAC.
33	TX_EN	input	GMII/MII transmit enable input.
34	RXD7	output	GMII receive data 7 output; not used in MII mode and driven low.
35	RXD6	output	GMII receive data 6 output; not used in MII mode and driven low.
36	DVDDL	power_in	1.2V digital VDD.
37	RXD5	output	GMII receive data 5 output; not used in MII mode and driven low.
38	RXD4	output	GMII receive data 4 output; not used in MII mode and driven low.
39	RXD3/MODE3	bidirectional	GMII/MII receive data 3 output, and MODE3 strap latched during power-up/reset.
40	DVDDH	power_in	3.3V or 2.5V digital VDD.
41	RXD2/MODE2	bidirectional	GMII/MII receive data 2 output, and MODE2 strap latched during power-up/reset.
42	DVDDL	power_in	1.2V digital VDD.
43	RXD1/MODE1	bidirectional	GMII/MII receive data 1 output, and MODE1 strap latched during power-up/reset.
44	RXD0/MODE0	bidirectional	GMII/MII receive data 0 output, and MODE0 strap latched during power-up/reset.
45	RX_DV/CLK125_EN	bidirectional	GMII/MII receive data valid output, and CLK125_EN strap (pull-up enables 125MHz clock output) latched during power-up/reset.
46	DVDDH	power_in	3.3V or 2.5V digital VDD.
47	RX_ER	output	GMII/MII receive error output.
48	RX_CLK/PHYAD2	bidirectional	GMII/MII receive reference clock output, and PHYAD[2] strap latched during power-up/reset.
49	CRS	output	GMII/MII carrier sense output.
50	MDC	input	Management data clock input (internal pull-up), reference clock for MDIO.
51	MDIO	bidirectional	Management data input/output (internal pull-up), synchronous to MDC; requires external pull-up to DVDDH of 1.0KΩ to 4.7KΩ.
52	COL	output	GMII/MII collision detected output.
53	INT_N	output	Programmable interrupt output; requires external pull-up to DVDDH of 1.0KΩ to 4.7KΩ when active low.
54	DVDDL	power_in	1.2V digital VDD.
55	CLK125_NDO/LED_MODE	bidirectional	125MHz reference clock output for the MAC, and LED_MODE strap latched during power-up/reset (pull-up = Single LED, pull-down = Tri-color Dual LED).
56	RESET_N	input	Chip reset, active low (internal pull-up); strap-ins are latched at the rising edge.
57	TX_CLK	output	MII transmit reference clock output.
58	LDO_O	output	On-chip 1.2V LDO controller output driving the gate of a P-channel MOSFET; can be left floating if 1.2V is provided by the system.
59	AVDDL_PLL	power_in	1.2V analog VDD for PLL.
60	XO	output	25MHz crystal feedback; no connect if oscillator or external clock source is used.
61	XI	input	Crystal/oscillator/external clock input, 25MHz +/-50ppm tolerance.
62	AVDDH	power_in	3.3V analog VDD.
63	ISET	bidirectional	Sets transmit output level; connect a 4.99KΩ 1% resistor to ground.
64	AGNDH	power_in	Analog ground.
65	P_GND	power_in	Exposed paddle on bottom of chip; connect to ground.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-64-EP(8x8)
Category	Interface
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Absolute maximum supply voltage (DVDDL, AVDDL, AVDDL_PLL)		-0.5			V	upper limit printed as VDD+10%	41
Absolute maximum supply voltage (AVDDH)		-0.5			V	upper limit printed as VDD+10%	41
Absolute maximum supply voltage (DVDDH)		-0.5			V	upper limit printed as VDD+10%	41
Absolute maximum input voltage (all inputs)		-0.5			V	upper limit printed as VDD+10%	41
Absolute maximum output voltage (all outputs)		-0.5			V	upper limit printed as VDD+10%	41
Lead temperature (soldering)				260	°C	soldering, 10 sec	41
Storage temperature	Ts	-55		150	°C		41
Supply voltage DVDDL, AVDDL, AVDDL_PLL		1.14		1.26	V		41
Supply voltage AVDDH		3.135		3.465	V		41
Supply voltage DVDDH @ 3.3V		3.135		3.465	V	DVDDH @ 3.3V	41
Supply voltage DVDDH @ 2.5V		2.375		2.625	V	DVDDH @ 2.5V	41
Ambient temperature TA (commercial, KSZ9021GN)	TA	0		70	°C	commercial KSZ9021GN	41
Maximum junction temperature	TJ			125	°C	TJ max	41
Peak differential output voltage (100Base-TX)	VO	0.95		1.05	V	100Ω termination across differential output	42
Input current	IIN	-10		10	µA	VIN = GND ~ VDDIO	42
Peak differential output voltage (10Base-T)	VP	2.2		2.8	V	100Ω termination across differential output	42
Rise/fall time	tr, tf	3		5	ns		42
Rise/fall time imbalance		0		0.5	ns		42
Duty cycle distortion		-0.25		0.25	ns		42
Output jitter peak-to-peak (100Base-TX)		0.7		1.4	ns		42
Squelch threshold (10Base-T receive)	VSQ	300		400	mV	5MHz square wave	42
GTX_CLK period (1000Base-T)	tcyc	7.5	8	8.5	ns	1000Base-T	44
ISET external resistor (nominal)	R(ISET)		4.99		KΩ	connect to ground on ISET pin	13
ISET external resistor tolerance		-1		1	%	1% resistor	13
Reference crystal/clock frequency			25		MHz	crystal or external clock on XI/XO	52
Reference crystal/clock frequency tolerance		-50		50	ppm	max frequency tolerance	52
Magnetics open-circuit inductance		350			μH	100mV, 100kHz, 8mA	52
Magnetics insertion loss				1	dB	0MHz, 100MHz	52
Magnetics HIPOT		1500			Vrms		52

CAD (KiCad official)

Symbol: KSZ9021GN
Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
3D model: QFN-64-EP(8x8) (KiCad packages3D, STEP)
3D model files: ksz9021gn-etched.step / ksz9021gn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz9021gn.step / ksz9021gn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (53 pp, sha256 2bb1c5d71e42069d, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF