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KSZ8895MLXI-TR

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Microchip Tech Interface - Specialized, LQFP-128(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ksz8895mlxi-trfactory-2.0.0extractor-text
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Contents

README

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KSZ8895MLXI-TR

Microchip Tech · Interface - Specialized · LQFP-128(14x14)

KSZ8895MLXI-TR from Microchip Tech, in a LQFP-128(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MDIXDIS input Disables auto MDI/MDI-X on all ports when pulled up; pull-down (default) gives normal operation.
2 GNDA power_in Analog ground.
3 VDDAR power_in 1.2V analog VDD.
4 RXP1 input Port 1 physical receive signal + (differential).
5 RXM1 input Port 1 physical receive signal - (differential).
6 GNDA power_in Analog ground.
7 TXP1 output Port 1 physical transmit signal + (differential).
8 TXM1 output Port 1 physical transmit signal - (differential).
9 VDDAT power_in 3.3V analog VDD.
10 RXP2 input Port 2 physical receive signal + (differential).
11 RXM2 input Port 2 physical receive signal - (differential).
12 GNDA power_in Analog ground.
13 TXP2 output Port 2 physical transmit signal + (differential).
14 TXM2 output Port 2 physical transmit signal - (differential).
15 VDDAR power_in 1.2V analog VDD.
16 GNDA power_in Analog ground.
17 ISET passive Sets physical transmit output current; pull down with a 12.4 kΩ 1% resistor.
18 VDDAT power_in 3.3V analog VDD.
19 RXP3 input Port 3 physical receive signal + (differential).
20 RXM3 input Port 3 physical receive signal - (differential).
21 GNDA power_in Analog ground.
22 TXP3 output Port 3 physical transmit signal + (differential).
23 TXM3 output Port 3 physical transmit signal - (differential).
24 VDDAT power_in 3.3V analog VDD.
25 RXP4 input Port 4 physical receive signal + (differential).
26 RXM4 input Port 4 physical receive signal - (differential).
27 GNDA power_in Analog ground.
28 TXP4 output Port 4 physical transmit signal + (differential).
29 TXM4 output Port 4 physical transmit signal - (differential).
30 GNDA power_in Analog ground.
31 VDDAR power_in 1.2V analog VDD.
32 RXP5 input Port 5 physical receive signal + (differential).
33 RXM5 input Port 5 physical receive signal - (differential).
34 GNDA power_in Analog ground.
35 TXP5 output Port 5 physical transmit signal + (differential).
36 TXM5 output Port 5 physical transmit signal - (differential).
37 VDDAT power_in 3.3V analog VDD.
38 NC unconnected No connection on MLX (FXSD3 fiber signal detect only on FQX).
39 NC unconnected No connection on MLX (FXSD4 fiber signal detect only on FQX).
40 NC unconnected No connection; leave floating.
41 NC unconnected No connection; leave floating.
42 NC unconnected No connection; leave floating.
43 NC unconnected No connection; leave floating.
44 NC unconnected No connection; leave floating.
45 NC unconnected No connection; leave floating.
46 NC unconnected No connection; leave floating.
47 PWRDN_N input Full-chip power down, active low, internal pull-up.
48 INTR_N output Interrupt output; open-drain pin with internal pull-up.
49 GNDD power_in Digital ground.
50 VDDC power_in 1.2V digital core VDD.
51 PMTXEN input PHY[5] MII transmit enable (internal pull-down).
52 PMTXD3 input PHY[5] MII transmit bit 3 (internal pull-down).
53 PMTXD2 input PHY[5] MII transmit bit 2 (internal pull-down).
54 PMTXD1 input PHY[5] MII transmit bit 1 (internal pull-down).
55 PMTXD0 input PHY[5] MII transmit bit 0 (internal pull-down).
56 PMTXER input PHY[5] MII transmit error (internal pull-down).
57 PMTXC bidirectional Output PHY[5] MII transmit clock on MLX.
58 GNDD power_in Digital ground.
59 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
60 PMRXC bidirectional Output PHY[5] MII receive clock on MLX.
61 PMRXDV bidirectional PHY[5] MII receive data valid; input with internal pull-down during reset, output otherwise.
62 PMRXD3 bidirectional PHY[5] MII receive bit 3; strap: PD (default) enables flow control, PU disables it.
63 PMRXD2 bidirectional PHY[5] MII receive bit 2; strap: PD (default) disables back pressure, PU enables it.
64 PMRXD1 bidirectional PHY[5] MII receive bit 1; strap: PD (default) drops excessive collision packets, PU does not.
65 PMRXD0 bidirectional PHY[5] MII receive bit 0; strap: PD (default) disables aggressive back-off in half-duplex, PU enables it.
66 PMRXER bidirectional PHY[5] MII receive error; strap: PD (default) packet size 1518/1522 bytes, PU 1536 bytes.
67 PCRS bidirectional PHY[5] MII carrier sense; port 4 strap: PD (default) force half-duplex, PU force full-duplex if auto-negotiation is disabled or fails.
68 PCOL bidirectional PHY[5] MII collision detect; port 4 strap: PD (default) no forced flow control, PU force flow control.
69 SMTXEN input Port 5 switch MII transmit enable (internal pull-down).
70 SMTXD3 input Port 5 switch MII transmit bit 3 (internal pull-down).
71 SMTXD2 input Port 5 switch MII transmit bit 2 (internal pull-down).
72 SMTXD1 input Port 5 switch MII transmit bit 1 (internal pull-down).
73 SMTXD0 input Port 5 switch MII transmit bit 0 (internal pull-down).
74 SMTXER input Port 5 switch MII transmit error (internal pull-down).
75 SMTXC bidirectional Port 5 switch MII transmit clock; input in SW5-MII MAC mode, output in PHY mode.
76 GNDD power_in Digital ground.
77 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
78 SMRXC bidirectional Port 5 switch MII receive clock; input in SW5-MII MAC mode, output in PHY mode.
79 SMRXDV bidirectional Switch MAC5 MII receive data valid; input with internal pull-down during reset, output otherwise.
80 SMRXD3 bidirectional Port 5 switch MII receive bit 3; strap: PD (default) disables SW5-MII full-duplex flow control, PU enables it.
81 SMRXD2 bidirectional Port 5 switch MII receive bit 2; strap: PD (default) full-duplex mode, PU half-duplex mode.
82 SMRXD1 bidirectional Port 5 switch MII receive bit 1; strap: PD (default) 100 Mbps mode, PU 10 Mbps mode.
83 SMRXD0 bidirectional Port 5 switch MII receive bit 0; strap selects LED mode: PD (default) mode 0, PU mode 1.
84 SCOL bidirectional Switch MII collision detect; input in SW5-MII MAC mode, output in PHY mode.
85 SCRS bidirectional Switch MII carrier sense; input in SW5-MII MAC mode, output in PHY mode.
86 SCONF1 input Dual MII configuration pin; with pins 91 and 87 sets Port 5 switch MAC5 and PHY5 MII modes (internal pull-down).
87 SCONF0 input Dual MII configuration pin; see pin 86 configuration table (internal pull-down).
88 GNDD power_in Digital ground.
89 VDDC power_in 1.2V digital core VDD.
90 LED5-2 bidirectional Port 5 LED indicator 2; strap: PU (default) aging enable, PD aging disable.
91 LED5-1 bidirectional Port 5 LED indicator 1; strap: PU (default) enables PHY[5] MII interface, PD tri-states PHY[5] MII outputs; also SCONF config bit.
92 LED5-0 bidirectional Port 5 LED indicator 0; port 4 strap: PU (default) enable auto-negotiation, PD disable.
93 LED4-2 bidirectional Port 4 LED indicator 2.
94 LED4-1 bidirectional Port 4 LED indicator 1.
95 LED4-0 bidirectional Port 4 LED indicator 0; strap: PU (default) normal mode, PD Energy Detection (EDPD) mode.
96 LED3-2 bidirectional Port 3 LED indicator 2.
97 LED3-1 bidirectional Port 3 LED indicator 1.
98 LED3-0 bidirectional Port 3 LED indicator 0; strap: PU (default) 8 mA I/O drive strength, PD 12 mA.
99 GNDD power_in Digital ground.
100 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
101 LED2-2 bidirectional Port 2 LED indicator 2; strap option applies to RQX only.
102 LED2-1 bidirectional Port 2 LED indicator 1; port 3 strap: PU (default) enable auto-negotiation, PD disable.
103 LED2-0 bidirectional Port 2 LED indicator 0.
104 LED1-2 bidirectional Port 1 LED indicator 2.
105 LED1-1 bidirectional Port 1 LED indicator 1; port 3 strap: PU (default) no forced flow control, PD force flow control.
106 LED1-0 bidirectional Port 1 LED indicator 0; port 3 strap: PU (default) force half-duplex, PD force full-duplex if auto-negotiation is disabled or fails.
107 MDC input MII management (MIIM) data clock for all PHYs, or SMI interface clock (internal pull-up).
108 MDIO bidirectional MII management data I/O or SMI interface data I/O; needs an external pull-up when driven.
109 SPIQ bidirectional SPI serial data output in SPI slave mode; needs an external pull-up when driven.
110 SPIC/SCL bidirectional SPI input clock up to 25 MHz in slave mode, or 61 kHz output clock in I2C master mode; needs an external pull-up when driven.
111 SPID/SDA bidirectional SPI serial data input in slave mode, or serial data I/O in I2C master mode; needs an external pull-up when driven.
112 SPIS_N input Active-low SPI slave select; high deselects the device and holds SPIQ high impedance, unused in I2C master mode.
113 PS1 input Serial bus configuration pin with PS0: 00 I2C master for EEPROM, 01 SMI, 10 SPI slave, 11 factory test (BIST).
114 PS0 input Serial bus configuration pin; see pin 113.
115 RST_N input Device reset, active low.
116 GNDD power_in Digital ground.
117 VDDC power_in 1.2V digital core VDD.
118 TESTEN input Factory test pin; NC for normal operation.
119 SCANEN input Factory test pin; NC for normal operation.
120 NC unconnected No connection; leave floating.
121 X1 input 25 MHz crystal connection or 3.3V oscillator input, ±50 ppm tolerance.
122 X2 output 25 MHz crystal clock connection.
123 NC unconnected No connection; leave floating.
124 NC unconnected No connection; leave floating.
125 LDO_O output Connects to MOSFET gate when using the internal 1.2V LDO controller; floating when using an external 1.2V LDO.
126 IN_PWR_SEL input Resistor-divider input enabling the internal 1.2V LDO controller (above 1V threshold); pull down to disable it for an external 1.2V LDO.
127 GNDA power_in Analog ground.
128 TEST2 unconnected Factory test pin; NC for normal operation.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-128(14x14)
Category Communication Interface Chip/UART/485/232
Pins 128

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDDAR, VDDC) VDDAR, VDDC 1.14 1.32 V Operating ratings 87
Supply Voltage (VDDAT) VDDAT 3.135 3.465 V Operating ratings 87
Supply Voltage (VDDIO @ 3.3V) VDDIO 3.135 3.465 V VDDIO @ 3.3V 87
Supply Voltage (VDDIO @ 2.5V) VDDIO 2.375 2.625 V VDDIO @ 2.5V 87
Supply Voltage (VDDIO @ 1.8V) VDDIO 1.71 1.89 V VDDIO @ 1.8V 87
Ambient Temperature (TA Industrial) TA -40 85 °C TA Industrial 87
Maximum Junction Temperature (TJ max.) TJ 125 °C 87
Supply Voltage (VDDAR, VDDAP, VDDC) VDDAR, VDDAP, VDDC -0.5 2.4 V Absolute maximum rating 87
Supply Voltage (VDDAT, VDDIO) VDDAT, VDDIO -0.5 4 V Absolute maximum rating 87
Input Voltage -0.5 4 V Absolute maximum rating 87
Output Voltage -0.5 4 V Absolute maximum rating 87
Lead Temperature 260 °C Soldering, 10s 87
Storage Temperature (TS) TS -55 150 °C Absolute maximum rating 87
HBM ESD Rating 5 kV Human body model, 1.5 kΩ in series with 100 pF 87
LQFP Thermal Resistance (ΘJA) ΘJA 48.22 °C/W 128-pin LQFP, no heat spreader, 0 m/s air velocity 87
LQFP Thermal Resistance (ΘJC) ΘJC 13.95 °C/W 128-pin LQFP, no heat spreader, 0 m/s air velocity 87
Input High Voltage (VDDIO = 3.3V) VIH 2 V VDDIO = 3.3V 89
Input High Voltage (VDDIO = 2.5V) VIH 1.8 V VDDIO = 2.5V 89
Input High Voltage (VDDIO = 1.8V) VIH 1.3 V VDDIO = 1.8V 89
Input Low Voltage (VDDIO = 3.3V) VIL 0.8 V VDDIO = 3.3V 89
Input Low Voltage (VDDIO = 2.5V) VIL 0.7 V VDDIO = 2.5V 89
Input Low Voltage (VDDIO = 1.8V) VIL 0.5 V VDDIO = 1.8V 89
Output High Voltage (VDDIO = 3.3V) VOH 2.4 V IOH = -8 mA, VDDIO = 3.3V 89
Output High Voltage (VDDIO = 2.5V) VOH 2 V IOH = -8 mA, VDDIO = 2.5V 89
Output High Voltage (VDDIO = 1.8V) VOH 1.5 V IOH = -8 mA, VDDIO = 1.8V 89
Output Low Voltage (VDDIO = 3.3V) VOL 0.4 V VIOL = 8 mA, VDDIO = 3.3V 89
Output Low Voltage (VDDIO = 2.5V) VOL 0.4 V VIOL = 8 mA, VDDIO = 2.5V 89
Output Low Voltage (VDDIO = 1.8V) VOL 0.3 V VIOL = 8 mA, VDDIO = 1.8V 89
Input Current (Excluding Pull-Up/Pull-Down) IIN -10 10 µA VIN = GND ~ VDDIO 89
Output Tri-State Leakage IOZ 10 µA VIN = GND ~ VDDIO 89
Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination on the differential output 89
Output Voltage Imbalance VIMB 2 % 100Ω termination on the differential output 89
Rise/Fall Time tr/tf 3 5 ns 89
Rise/Fall Time Imbalance 0 0.5 ns 89
Duty Cycle Distortion -0.5 0.5 ns 89
Overshoot 5 % 89
Output Jitters (100BASE-TX/FX) 0.75 1.4 ns Peak-to-Peak 89
Input Signal Threshold Voltage (100BASE-FX Receiver) VIST 400 mV 100Ω impedance on RX± 89
Squelch Threshold (10BASE-T Receive) VSQ 300 400 585 mV 5 MHz square wave 89
Peak Differential Output Voltage (10BASE-T) VP 2.2 2.5 2.8 V 100Ω termination on the differential output; VDDAT = 3.3V 89
Output Jitters (10BASE-T) 1.4 3.5 ns Peak-to-Peak; VDDAT = 3.3V 89
Rise/Fall Times (10BASE-T) 28 30 ns VDDAT = 3.3V 89
Setup Time (EEPROM) tS1 20 ns 90
Hold Time (EEPROM) tH1 20 ns 90
Output Valid (EEPROM) tOV1 4096 4112 4128 ns 90

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper FQX: This pin can be floating when port 3 is used as copper port 9

CAD (KiCad official)

  • Symbol: KSZ8895MLXI-TR
  • Footprint: Package_QFP:LQFP-128_14x14mm_P0.4mm
  • 3D model: LQFP-128(14x14) (KiCad packages3D, STEP)
  • 3D model files: ksz8895mlxi-tr-etched.step / ksz8895mlxi-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8895mlxi-tr.step / ksz8895mlxi-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (108 pp, sha256 cdc8a1ad0e708814, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF