KSZ8895FQXI from Microchip Tech, in a QFP-128(14x20). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	MDI-XDIS	input	Disables auto MDI/MDI-X on all ports when pulled up; pull-down (default) gives normal operation.
2	GNDA	power_in	Analog ground.
3	VDDAR	power_in	1.2V analog VDD.
4	RXP1	input	Port 1 physical receive signal + (differential).
5	RXM1	input	Port 1 physical receive signal - (differential).
6	GNDA	power_in	Analog ground.
7	TXP1	output	Port 1 physical transmit signal + (differential).
8	TXM1	output	Port 1 physical transmit signal - (differential).
9	VDDAT	power_in	3.3V analog VDD.
10	RXP2	input	Port 2 physical receive signal + (differential).
11	RXM2	input	Port 2 physical receive signal - (differential).
12	GNDA	power_in	Analog ground.
13	TXP2	output	Port 2 physical transmit signal + (differential).
14	TXM2	output	Port 2 physical transmit signal - (differential).
15	VDDAR	power_in	1.2V analog VDD.
16	GNDA	power_in	Analog ground.
17	ISET	passive	Sets the physical transmit output current; pull down with a 12.4 kΩ 1% resistor.
18	VDDAT	power_in	3.3V analog VDD.
19	RXP3	input	Port 3 physical receive signal + (differential).
20	RXM3	input	Port 3 physical receive signal - (differential).
21	GNDA	power_in	Analog ground.
22	TXP3	output	Port 3 physical transmit signal + (differential).
23	TXM3	output	Port 3 physical transmit signal - (differential).
24	VDDAT	power_in	3.3V analog VDD.
25	RXP4	input	Port 4 physical receive signal + (differential).
26	RXM4	input	Port 4 physical receive signal - (differential).
27	GNDA	power_in	Analog ground.
28	TXP4	output	Port 4 physical transmit signal + (differential).
29	TXM4	output	Port 4 physical transmit signal - (differential).
30	GNDA	power_in	Analog ground.
31	VDDAR	power_in	1.2V analog VDD.
32	RXP5	input	Port 5 physical receive signal + (differential).
33	RXM5	input	Port 5 physical receive signal - (differential).
34	GNDA	power_in	Analog ground.
35	TXP5	output	Port 5 physical transmit signal + (differential).
36	TXM5	output	Port 5 physical transmit signal - (differential).
37	VDDAT	power_in	3.3V analog VDD.
38	NC/FXSD3	input	Port 3 fiber signal detect when Register 239 bit [7] sets fiber mode; can float when port 3 is copper (default).
39	FXSD4	input	Fiber signal detect pin for Port 4.
40	NC	unconnected	No connection; leave floating.
41	NC	unconnected	No connection; leave floating.
42	NC	unconnected	No connection; leave floating.
43	NC	unconnected	No connection; leave floating.
44	NC	unconnected	No connection; leave floating.
45	NC	unconnected	No connection; leave floating.
46	NC	unconnected	No connection; leave floating.
47	PWRDN_N	input	Active-low full-chip power down (internal pull-up).
48	INTR_N	output	Interrupt output; open-drain pin with internal pull-up.
49	GNDD	power_in	Digital ground.
50	VDDC	power_in	1.2V digital core VDD.
51	PMTXEN	input	PHY [5] MII transmit enable.
52	PMTXD3	input	PHY [5] MII transmit bit 3.
53	PMTXD2	input	PHY [5] MII transmit bit 2.
54	PMTXD1	input	PHY [5] MII transmit bit 1.
55	PMTXD0	input	PHY [5] MII transmit bit 0.
56	PMTXER	input	PHY [5] MII transmit error.
57	PMTXC/PMREFCLK	output	On the FQX, PHY [5] MII transmit clock output.
58	GNDD	power_in	Digital ground.
59	VDDIO	power_in	3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
60	PMRXC	output	PHY [5] MII receive clock output.
61	PMRXDV/PMCRSDV	output	PHY [5] MII receive data valid (PMRXDV on the FQX); internal pull-down during reset.
62	PMRXD3	bidirectional	PHY [5] MII receive bit 3; strap: PD (default) enables flow control, PU disables it.
63	PMRXD2	bidirectional	PHY [5] MII receive bit 2; strap: PD (default) disables back pressure, PU enables it.
64	PMRXD1	bidirectional	PHY [5] MII receive bit 1; strap: PD (default) drops excessive collision packets, PU does not.
65	PMRXD0	bidirectional	PHY [5] MII receive bit 0; strap: PD (default) disables aggressive back-off in half-duplex, PU enables it.
66	PMRXER	bidirectional	PHY [5] MII receive error; strap: PD (default) packet size 1518/1522 bytes, PU 1536 bytes.
67	PCRS	bidirectional	PHY [5] MII carrier sense; port 4 strap: PD (default) force half-duplex, PU force full-duplex if auto-negotiation is disabled or fails (Register 76).
68	PCOL	bidirectional	PHY [5] MII collision detect; port 4 strap: PD (default) no forced flow control, PU force flow control (Register 66).
69	SMTXEN	input	Port 5 Switch MII transmit enable.
70	SMTXD3	input	Port 5 Switch MII transmit bit 3.
71	SMTXD2	input	Port 5 Switch MII transmit bit 2.
72	SMTXD1	input	Port 5 Switch MII transmit bit 1.
73	SMTXD0	input	Port 5 Switch MII transmit bit 0.
74	SMTXER	input	Port 5 Switch MII transmit error.
75	SMTXC/SMREFCLK	bidirectional	Port 5 Switch MII transmit clock; input in SW5-MII MAC mode, output in PHY modes.
76	GNDD	power_in	Digital ground.
77	VDDIO	power_in	3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
78	SMRXC	bidirectional	Port 5 Switch MII receive clock; input in SW5-MII MAC mode, output in PHY mode.
79	SMRXDV/SMCRSDV	output	Switch MAC5 MII receive data valid (SMRXDV on the FQX); internal pull-down during reset.
80	SMRXD3	bidirectional	Port 5 Switch MII receive bit 3; strap: PD (default) disables SW5-MII full-duplex flow control, PU enables it.
81	SMRXD2	bidirectional	Port 5 Switch MII receive bit 2; strap: PD (default) full-duplex mode, PU half-duplex mode.
82	SMRXD1	bidirectional	Port 5 Switch MII receive bit 1; strap: PD (default) 100 Mbps mode, PU 10 Mbps mode.
83	SMRXD0	bidirectional	Port 5 Switch MII receive bit 0; strap selects LED mode, PD (default) mode 0, PU mode 1 (Register 11).
84	SCOL	bidirectional	Port switch MII collision detect; input in SW5-MII MAC modes, output in PHY modes.
85	SCRS	bidirectional	Port switch MII carrier sense; input in SW5-MII MAC modes, output in PHY modes.
86	SCONF1	input	Dual MII configuration pin; with pins 91 and 87 selects Port 5 switch MAC5 and PHY5 MII modes (internal pull-down).
87	SCONF0	input	Dual MII configuration pin; see pin 86 configuration table (internal pull-down).
88	GNDD	power_in	Digital ground.
89	VDDC	power_in	1.2V digital core VDD.
90	LED5-2	bidirectional	Port 5 LED indicator 2; strap: PU (default) aging enable, PD aging disable.
91	LED5-1	bidirectional	Port 5 LED indicator 1; strap: PU (default) enables PHY [5] MII interface, PD tri-states all PHY [5] MII outputs.
92	LED5-0	bidirectional	Port 5 LED indicator 0; port 4 strap: PU (default) enables auto-negotiation, PD disables it (Register 76 bit [7]).
93	LED4-2	output	Port 4 LED indicator 2.
94	LED4-1	output	Port 4 LED indicator 1.
95	LED4-0	bidirectional	Port 4 LED indicator 0; strap: PU (default) normal mode, PD Energy Detection (EDPD) mode (Register 14 bits [4:3]).
96	LED3-2	output	Port 3 LED indicator 2.
97	LED3-1	output	Port 3 LED indicator 1.
98	LED3-0	bidirectional	Port 3 LED indicator 0; strap: PU (default) 8 mA I/O drive strength, PD 12 mA (Register 132 bits [7:6]).
99	GNDD	power_in	Digital ground.
100	VDDIO	power_in	3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
101	LED2-2	bidirectional	Port 2 LED indicator 2; strap option applies to the RQX only.
102	LED2-1	bidirectional	Port 2 LED indicator 1; port 3 strap: PU (default) enables auto-negotiation, PD disables it (Register 60 bit [7]).
103	LED2-0	output	Port 2 LED indicator 0.
104	LED1-2	output	Port 1 LED indicator 2.
105	LED1-1	bidirectional	Port 1 LED indicator 1; port 3 strap: PU (default) no forced flow control, PD force flow control (Register 60 bit [4]).
106	LED1-0	bidirectional	Port 1 LED indicator 0; port 3 strap: PU (default) force half-duplex, PD force full-duplex if auto-negotiation is disabled or fails (Register 60 bit [5]).
107	MDC	input	All-PHYs MII management (MIIM) data clock, or SMI interface clock.
108	MDIO	bidirectional	All-PHYs MII management (MIIM) data I/O, or SMI interface data I/O; needs an external pull-up when driven.
109	SPIQ	output	SPI serial data output in SPI slave mode; needs an external pull-up when driven.
110	SPIC/SCL	bidirectional	Input clock up to 25 MHz in SPI slave mode, or 61 kHz output clock in I2C master mode; needs an external pull-up when driven.
111	SPID/SDA	bidirectional	Serial data input in SPI slave mode, or serial data input/output in I2C master mode; needs an external pull-up when driven.
112	SPIS_N	input	Active-low SPI slave select; high deselects the device and holds SPIQ high impedance, a high-to-low transition starts an SPI transfer; unused in I2C master mode.
113	PS1	input	Serial bus configuration pin PS[1]; PS[1:0] = 00 I2C master (EEPROM), 01 SMI, 10 SPI slave, 11 factory test (BIST).
114	PS0	input	Serial bus configuration pin PS[0]; see pin 113.
115	RST_N	input	Active-low device reset.
116	GNDD	power_in	Digital ground.
117	VDDC	power_in	1.2V digital core VDD.
118	TESTEN	input	Factory test pin; NC for normal operation.
119	SCANEN	input	Factory test pin; NC for normal operation.
120	NC	unconnected	No connection; leave floating.
121	X1	input	25 MHz crystal connection or 3.3V oscillator input, ±50 ppm tolerance.
122	X2	output	25 MHz crystal clock connection.
123	NC	unconnected	No connection; leave floating.
124	NC	unconnected	No connection; leave floating.
125	LDO_O	output	Connects to the MOSFET gate when using the internal 1.2V LDO controller; floating when using an external 1.2V LDO.
126	IN_PWR_SEL	input	Resistor-divider input that enables the internal 1.2V LDO controller above 1V; pull down to disable it when using an external 1.2V LDO.
127	GNDA	power_in	Analog ground.
128	TEST2	unconnected	Factory test pin; NC for normal operation.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFP-128(14x20)
Category	Communication Interface Chip/UART/485/232
Pins	128

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDDAR, VDDAP, VDDC		-0.5		2.4	V		87
Supply voltage VDDAT, VDDIO		-0.5		4	V		87
Input voltage		-0.5		4	V		87
Output voltage		-0.5		4	V		87
Lead temperature				260	°C	soldering, 10s	87
Storage temperature	TS	-55		150	°C		87
HBM ESD rating				5	kV	Human body model, 1.5 kΩ in series with 100 pF	87
Supply voltage VDDAR, VDDC	VDDAR, VDDC	1.14		1.32	V		87
Supply voltage VDDAT	VDDAT	3.135		3.465	V		87
Supply voltage VDDIO @ 3.3V	VDDIO	3.135		3.465	V	VDDIO @ 3.3V	87
Supply voltage VDDIO @ 2.5V	VDDIO	2.375		2.625	V	VDDIO @ 2.5V	87
Supply voltage VDDIO @ 1.8V	VDDIO	1.71		1.89	V	VDDIO @ 1.8V	87
Ambient temperature (Industrial)	TA	-40		85	°C	TA Industrial	87
Maximum junction temperature	TJ max			125	°C		87
PQFP thermal resistance junction to ambient	ΘJA		41.54		°C/W	No heat spreader, air velocity 0 m/s	87
PQFP thermal resistance junction to case	ΘJC		19.78		°C/W	No heat spreader, air velocity 0 m/s	87
Input high voltage, VDDIO = 3.3V	VIH	2			V	VDDIO = 3.3V	89
Input high voltage, VDDIO = 2.5V	VIH	1.8			V	VDDIO = 2.5V	89
Input high voltage, VDDIO = 1.8V	VIH	1.3			V	VDDIO = 1.8V	89
Input low voltage, VDDIO = 3.3V	VIL			0.8	V	VDDIO = 3.3V	89
Input low voltage, VDDIO = 2.5V	VIL			0.7	V	VDDIO = 2.5V	89
Input low voltage, VDDIO = 1.8V	VIL			0.5	V	VDDIO = 1.8V	89
Input current (excluding pull-up/pull-down)	IIN	-10		10	µA	VIN = GND ~ VDDIO	89
Output high voltage, VDDIO = 3.3V	VOH	2.4			V	IOH = -8 mA, VDDIO = 3.3V	89
Output high voltage, VDDIO = 2.5V	VOH	2			V	IOH = -8 mA, VDDIO = 2.5V	89
Output high voltage, VDDIO = 1.8V	VOH	1.5			V	IOH = -8 mA, VDDIO = 1.8V	89
Output low voltage, VDDIO = 3.3V	VOL			0.4	V	IOL = 8 mA, VDDIO = 3.3V	89
Output low voltage, VDDIO = 2.5V	VOL			0.4	V	IOL = 8 mA, VDDIO = 2.5V	89
Output low voltage, VDDIO = 1.8V	VOL			0.3	V	IOL = 8 mA, VDDIO = 1.8V	89
Output tri-state leakage	IOZ			10	µA	VIN = GND ~ VDDIO	89
100BASE-TX/FX peak differential output voltage	VO	0.95		1.05	V	100Ω termination on the differential output	89
100BASE-TX/FX output voltage imbalance	VIMB			2	%	100Ω termination on the differential output	89
100BASE-TX/FX rise/fall time	tr/tf	3		5	ns		89
100BASE-TX/FX rise/fall time imbalance		0		0.5	ns		89
100BASE-TX/FX duty cycle distortion		-0.5		0.5	ns		89
100BASE-TX/FX overshoot				5	%		89
100BASE-TX/FX output jitters		0	0.75	1.4	ns	Peak-to-Peak	89
100BASE-FX input signal threshold voltage	VIST	400			mV	100Ω impedance on RX±	89
10BASE-T squelch threshold	VSQ	300	400	585	mV	5 MHz square wave	89
10BASE-T peak differential output voltage	VP	2.2	2.5	2.8	V	100Ω termination on the differential output, VDDAT = 3.3V	89
10BASE-T output jitters			1.4	3.5	ns	Peak-to-Peak, VDDAT = 3.3V	89
10BASE-T rise/fall times			28	30	ns	VDDAT = 3.3V	89
EEPROM setup time	tS1	20			ns		90
EEPROM hold time	tH1	20			ns		90
EEPROM output valid	tOV1	4096	4112	4128	ns		90
EEPROM clock cycle	tCYC1		16384		ns		90
Reference crystal frequency tolerance		-50		50	ppm	25.00000 MHz crystal, max	100
100BASE-TX 3.3V analog current	IDX		86		mA	VDDAT, all ports 100% utilization	88
100BASE-TX 1.2V analog current	IDda		22		mA	VDDAR, all ports 100% utilization	88
100BASE-TX 1.2V digital current	IDDc		42		mA	VDDC, all ports 100% utilization	88
10BASE-T 3.3V analog current	IDX		107		mA	VDDAT, all ports 100% utilization	88
Hardware power-down current 3.3V	IHPDM1		2		mA	VDDAT + VDDIO	88
Hardware power-down current 1.2V	IHPDM2		1		mA	VDDAR + VDDC	88

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part	Material	Colour / plating	Datasheet says	Page
contacts	copper		FQX: This pin can be floating when port 3 is used as copper port	9

CAD (KiCad official)

Symbol: KSZ8895FQXI
Footprint: Package_QFP:LQFP-128_14x20mm_P0.5mm
3D model: QFP-128(14x20) (KiCad packages3D, STEP)
3D model files: ksz8895fqxi-etched.step / ksz8895fqxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8895fqxi.step / ksz8895fqxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (108 pp, sha256 cdc8a1ad0e708814, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

KSZ8895FQXI

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3D Model

Symbol & Footprint

Schematic Symbol

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Datasheet

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