KSZ8873MML from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RXM1	bidirectional	Port 1 physical receive or transmit signal (- differential).
2	RXP1	bidirectional	Port 1 physical receive or transmit signal (+ differential).
3	AGND	power_in	Analog ground.
4	TXM1	bidirectional	Port 1 physical transmit or receive signal (- differential).
5	TXP1	bidirectional	Port 1 physical transmit or receive signal (+ differential).
6	VDDA_3.3	power_in	3.3V analog VDD.
7	AGND	power_in	Analog ground.
8	ISET	output	Sets physical transmit output current; pull down to ground with an 11.8kΩ 1% resistor.
9	VDDA_1.8	power_in	1.8V analog core power input from VDDCO (pin 56).
10	RXM2	bidirectional	Port 2 physical receive or transmit signal (- differential).
11	RXP2	bidirectional	Port 2 physical receive or transmit signal (+ differential).
12	AGND	power_in	Analog ground.
13	TXM2	bidirectional	Port 2 physical transmit or receive signal (- differential).
14	TXP2	bidirectional	Port 2 physical transmit or receive signal (+ differential).
15	FXSD2	input	For MLL/RLL, connect to analog ground by pull-down resistor (fiber signal detect/factory test pin on FLL).
16	PWRDN	input	Chip power down input, active-low, with internal pull-up.
17	X1	input	25 MHz or 50 MHz crystal/oscillator connection (±50 ppm); with an oscillator, X1 takes a 3.3V tolerant oscillator and clock must be applied before reset goes high.
18	X2	output	Crystal connection for the 25 MHz or 50 MHz clock; NC when an oscillator is used on X1.
19	SMTXEN3	input	Switch MII transmit enable, with internal pull-up.
20	SMTXD33/EN_REFCLKO_3	input	MLL/FLL: switch MII transmit data bit 3 (internal pull-up); on RLL a strap option enabling REFCLKO_3 output.
21	SMTXD32	input	MLL/FLL: switch MII transmit data bit 2, with internal pull-up (no connection on RLL).
22	SMTXD31	input	Switch MII/RMII transmit data bit 1, with internal pull-up.
23	SMTXD30	input	Switch MII/RMII transmit data bit 0, with internal pull-up.
24	GND	power_in	Digital ground.
25	VDDIO	power_in	3.3V, 2.5V, or 1.8V digital VDD input supply for IO, with well decoupling capacitors.
26	SMTXC3/REFCLKI_3	bidirectional	MLL/FLL: switch MII transmit clock, output in PHY MII and SNI mode, input in MAC MII mode (RLL: RMII reference clock input).
27	SMTXER3/MII_LINK_3	input	Switch MII transmit error; in MII PHY mode 0 = link from host, 1 = no link on port 3 and enables bypass mode (internal pull-down).
28	SMRXDV3	bidirectional	Switch MII receive data valid; strap option for MII mode: PU = PHY mode, PD = MAC mode.
29	SMRXD33/REFCLKO_3	bidirectional	MLL/FLL: switch MII receive data bit 3; strap option enabling auto-negotiation on port 2 (PU = enable, PD = disable).
30	SMRXD32	bidirectional	Switch MII receive data bit 2; strap to force port 2 speed when P2ANEN = 0 (PU = 100BT, PD = 10BT).
31	SMRXD31	bidirectional	Switch MII/RMII receive data bit 1; strap to force port 2 duplex (PU = full, PD = half).
32	GND	power_in	Digital ground.
33	SMRXD30	bidirectional	Switch MII/RMII receive data bit 0; strap for port 2 flow control (PU = always enabled, PD = determined by auto-negotiation).
34	SCRS3/NC	bidirectional	MLL/FLL: switch MII carrier sense (RLL: no connection, internal pull-up); in MAC mode drive from PHY CRS, or pull down with 1kΩ if only full-duplex.
35	SCOL3/NC	bidirectional	MLL/FLL: switch MII collision detect (RLL: no connection, internal pull-up).
36	SMRXC3/NC	bidirectional	MLL/FLL: switch MII receive clock, output in PHY MII mode and input in MAC MII mode (RLL: no connection).
37	GND	power_in	Digital ground.
38	VDDC	power_in	1.8V digital core power input from VDDCO (pin 56).
39	SPIQ	bidirectional	SPI slave mode serial data output (external pull-up needed when in use); strap for XCLK frequency: PU = 25 MHz, PD = 50 MHz.
40	SPISN	input	SPI slave mode chip select, active-low; high deselects the device and tri-states SPIQ; external pull-up needed when in use.
41	INTRN	output	Active-low interrupt to host CPU indicating an interrupt status bit is set on lost link (registers 187 and 188).
42	SCL_MDC	bidirectional	Clock input in SPI/I2C slave mode and MIIM, clock output in I2C master mode.
43	SDA_MDIO	bidirectional	SPI slave serial data input, I2C serial data input/output, or MIIM data input/output; external pull-up needed when in use.
44	NC	unconnected	Unused pin; only this NC pin may be pulled down by a resistor for better EMI.
45	P1ANEN	bidirectional	Strap to enable (PU) or disable (PD) auto-negotiation on port 1.
46	P1SPD	bidirectional	Strap to force port 1 to 100BT (PU) or 10BT (PD) if P1ANEN = 0.
47	P1DPX	bidirectional	Strap selecting port 1 full-duplex (PU) or half-duplex (PD) default or forced mode.
48	GND	power_in	Digital ground.
49	VDDC	power_in	1.8V digital core power input from VDDCO (pin 56).
50	P1FFC	bidirectional	Strap: PU = always force port 1 flow control, PD = determined by auto-negotiation result.
51	P3SPD	bidirectional	Strap: PU = force port 3 to 10BT, PD = force port 3 to 100BT (default).
52	NC	unconnected	Unused pin, no external connection.
53	NC	unconnected	Unused pin, no external connection.
54	VDDIO	power_in	3.3V, 2.5V or 1.8V digital VDD input supply for IO, with well decoupling capacitors.
55	GND	power_in	Digital ground.
56	VDDCO	power_out	1.8V core output from internal LDO (input from VDDIO) powering VDDA_1.8 and VDDC; do not connect an external supply, and use a ferrite bead between analog and digital 1.8V.
57	NC	unconnected	Unused pin, no external connection.
58	P1LED1	bidirectional	Port 1 LED indicator (default speed); strap for port 3 flow control: PU = force enabled (default), PD = disable.
59	P1LED0	bidirectional	Port 1 LED indicator (default link/activity); strap for port 3 duplex: PU = half, PD = full (default); external 0.5 kΩ pull-down recommended.
60	P2LED1	bidirectional	Port 2 LED indicator (default speed); with P2LED0 straps serial bus mode: [P2LED1,P2LED0] 00 = I2C master, 01 = I2C slave, 10 = SPI slave, 11 = SMI/MIIM.
61	P2LED0	bidirectional	Port 2 LED indicator (default link/activity); with P2LED1 straps the serial bus configuration mode.
62	RSTN	input	Hardware reset, active-low, with internal pull-up.
63	FXSD1	input	For MLL/RLL, connect to analog ground by pull-down resistor (fiber signal detect on FLL).
64	VDDA_1.8	power_in	1.8V analog VDD input from VDDCO (pin 56) through external ferrite bead and capacitors.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	LQFP-64(10x10)
Category	Communication Interface Chip/UART/485/232
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage VDDA_1.8, VDDC (abs max)	VIN	-0.5		2.4	V	VDDA_1.8, VDDC	74
Supply Voltage VDDA_3.3, VDDIO (abs max)	VIN	-0.5		4	V	VDDA_3.3, VDDIO	74
Input Voltage		-0.5		4	V		74
Output Voltage		-0.5		4	V		74
Lead Temperature				260	°C	soldering, 10s	74
Storage Temperature	TS	-55		150	°C		74
HBM ESD Rating		-3		3	kV		74
Supply Voltage VDDA_1.8, VDDC (operating)		1.66		1.94	V	VDDA_1.8, VDDC	74
Supply Voltage VDDA_3.3 (operating)		2.5		3.465	V	VDDA_3.3	74
Supply Voltage VDDIO (operating)		1.71		3.465	V	VDDIO	74
Ambient Temperature (Industrial)	TA	-40		85	°C	Industrial	74
Ambient Temperature (Commercial)	TA	0		70	°C	Commercial	74
Junction Temperature	TJ			125	°C		74
Thermal Resistance LQFP	ΘJA		47.24		°C/W	No heat spreader	74
Thermal Resistance LQFP	ΘJC		19.37		°C/W	No heat spreader	74
Input High Voltage	VIH	2			V	VDDIO = 3.3V (2.0/1.8/1.3 for 3.3/2.5/1.8V)	75
Input Low Voltage	VIL			0.8	V	VDDIO = 3.3V (0.8/0.7/0.5 for 3.3/2.5/1.8V)	75
Input Current	IIN	-10		10	µA	VIN = GND ~ VDDIO	75
Output High Voltage	VOH	2.4			V	IOH = -8 mA (2.4/2.0/1.5 for 3.3/2.5/1.8V)	75
Output Low Voltage	VOL			0.4	V	IOL = 8 mA (0.4/0.4/0.3 for 3.3/2.5/1.8V)	75
Output Tri-State Leakage	/IOZ/			10	µA		75
Peak Differential Output Voltage (100BASE-TX)	VO	0.95		1.05	V	100Ω termination across differential output	75
Output Voltage Imbalance	VIMB			2	%	100Ω termination across differential output	76
Rise/Fall Time	tr/tf	3		5	ns		76
Rise/Fall Time Imbalance		0		0.5	ns		76
Duty Cycle Distortion		-0.5		0.5	ns		76
Overshoot				5	%		76
Output Jitter (100BASE-TX)			0.7	1.4	ns	Peak-to-peak	76
Output Jitter (10BASE-T)			1.4	11	ns	Peak-to-peak	76
Setup time	ts1	20			ns		77
Hold time	th1	20			ns		77
Output valid	tov1	4096	4112	4128	ns		77
Clock cycle	tcyc1		16384		ns		77
100BASE-TX current, single supply	IDDXIO		115		mA	VDDA_3.3, VDDIO = 3.3V (single power), internal 1.8V LDO	75
10BASE-T current, single supply	IDDXIO		85		mA	VDDA_3.3, VDDIO = 3.3V	75
Power Saving Mode current	IDD3		96		mA	VDDA_3.3, VDDIO = 3.3V, Unplug Port 1 and Port 2, Set Register 195 bit[1,0] = [1,1]	75
Soft Power Down Mode current	IDD4		5		mA	VDDA_3.3, VDDIO = 3.3V, Set Register 195 bit[1,0] = [1,0]	75
Energy Detect Mode current	IDD5		15		mA	VDDA_3.3, VDDIO = 3.3V, Unplug Port 1 and Port 2	75
10BASE-T Squelch Threshold	VSQ		400		mV	5 MHz square wave	76
10BASE-T Peak Differential Output Voltage	VP		2.4		V	100Ω termination across differential output	76

CAD (KiCad official)

Symbol: KSZ8873MML
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ksz8873mml-etched.step / ksz8873mml-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8873mml.step / ksz8873mml.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (95 pp, sha256 5bfa1107d97e8afb, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

KSZ8873MML

Verified KSZ8873MML

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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