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KSZ8873MLL

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Microchip Tech Interface - Specialized, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ksz8873mllfactory-2.0.0extractor-text
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Contents

README

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KSZ8873MLL

Microchip Tech · Interface - Specialized · LQFP-64(10x10)

KSZ8873MLL from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXM1 bidirectional Physical receive or transmit signal (negative differential) for port 1.
2 RXP1 bidirectional Physical receive or transmit signal (positive differential) for port 1.
3 AGND power_in Analog ground.
4 TXM1 bidirectional Physical transmit or receive signal (negative differential) for port 1.
5 TXP1 bidirectional Physical transmit or receive signal (positive differential) for port 1.
6 VDDA_3.3 power_in 3.3V analog VDD for the transceiver.
7 AGND power_in Analog ground.
8 ISET output Sets the physical transmit output current; pull down with an 11.8 kohm 1% resistor to ground.
9 VDDA_1.8 power_in 1.8V analog core power input from VDDCO (pin 56).
10 RXM2 bidirectional Physical receive or transmit signal (negative differential) for port 2.
11 RXP2 bidirectional Physical receive or transmit signal (positive differential) for port 2.
12 AGND power_in Analog ground.
13 TXM2 bidirectional Physical transmit or receive signal (negative differential) for port 2.
14 TXP2 bidirectional Physical transmit or receive signal (positive differential) for port 2.
15 FXSD2 input MLL/RLL: connect to analog ground by pull-down resistor; FLL: fiber signal detect / factory test pin.
16 PWRDN input Chip power-down input, active-low, with internal pull-up.
17 X1 input 25 MHz or 50 MHz crystal/oscillator clock input; clock is +/-50 ppm and must be applied before reset voltage goes high.
18 X2 output Crystal connection for X1; NC when an oscillator drives X1.
19 SMTXEN3 input Switch MII transmit enable for port 3, with internal pull-up.
20 SMTXD33/EN_REFCLKO_3 input MLL/FLL: switch MII transmit data bit 3; RLL: strap for RMII REFCLKO_3 output enable (pull-up enables, pull-down disables).
21 SMTXD32/NC input MLL/FLL: switch MII transmit data bit 2 with internal pull-up; RLL: no connection.
22 SMTXD31 input Switch MII/RMII transmit data bit 1, with internal pull-up.
23 SMTXD30 input Switch MII/RMII transmit data bit 0, with internal pull-up.
24 GND power_in Digital ground.
25 VDDIO power_in 3.3V, 2.5V, or 1.8V digital IO supply input; requires well-decoupled capacitors.
26 SMTXC3/REFCLKI_3 bidirectional MII transmit clock (output in PHY and SNI mode, input in MAC MII and RMII mode); RLL: RMII reference clock input.
27 SMTXER3/MII_LINK_3 input MII transmit error in MII mode; doubles as MII link indicator from host (high = no link) for bypass mode, with internal pull-down.
28 SMRXDV3 bidirectional Switch MII receive data valid; strap selects PHY mode (pull-up) or MAC mode (pull-down).
29 SMRXD33/REFCLKO_3 bidirectional MLL/FLL: switch MII receive data bit 3; RLL: 50 MHz reference clock output in RMII mode; strap enables P2ANEN.
30 SMRXD32 bidirectional Switch MII receive data bit 2; strap forces port 2 speed (pull-up 100BT, pull-down 10BT when P2ANEN=0).
31 SMRXD31 bidirectional Switch MII/RMII receive data bit 1; strap sets port 2 duplex mode (P2DPX).
32 GND power_in Digital ground.
33 SMRXD30 bidirectional Switch MII/RMII receive data bit 0; strap forces port 2 flow control (P2FFC).
34 SCRS3/NC bidirectional MLL/FLL: switch MII carrier sense; RLL: no connection with internal pull-up. Pull down with 1 kohm if only full-duplex is used.
35 SCOL3/NC bidirectional MLL/FLL: switch MII collision detect; RLL: no connection with internal pull-up.
36 SMRXC3/NC bidirectional MLL/FLL: switch MII receive clock (output in PHY mode, input in MAC mode); RLL: no connection.
37 GND power_in Digital ground.
38 VDDC power_in 1.8V digital core power input from VDDCO (pin 56).
39 SPIQ bidirectional SPI slave serial data output (needs external pull-up when used); strap selects XCLK frequency (pull-up 25 MHz, pull-down 50 MHz).
40 SPISN input SPI slave chip select, active-low; high deselects the device and tri-states SPIQ. Needs external pull-up when used.
41 INTRN output Active-low interrupt output to the host CPU, signalling a status bit set on lost link (see registers 187 and 188).
42 SCL_MDC bidirectional SPI/I2C slave clock input, I2C master clock output, or MIIM clock input depending on mode.
43 SDA_MDIO bidirectional SPI slave data input, I2C data I/O, or MIIM data I/O depending on mode; needs external pull-up when used.
44 NC unconnected Unused pin; the only NC pin that may be pulled down by a resistor for better EMI.
45 P1ANEN bidirectional Strap: pull-up enables auto-negotiation on port 1, pull-down disables it.
46 P1SPD bidirectional Strap: pull-up forces port 1 to 100BT and pull-down forces 10BT when P1ANEN=0.
47 P1DPX bidirectional Strap: sets port 1 duplex default if auto-negotiation fails (pull-up full, pull-down half) or forces duplex when P1ANEN=0.
48 GND power_in Digital ground.
49 VDDC power_in 1.8V digital core power input from VDDCO (pin 56).
50 P1FFC bidirectional Strap: pull-up always enables port 1 flow control; pull-down lets auto-negotiation decide.
51 P3SPD bidirectional Strap: pull-up forces port 3 to 10BT; pull-down forces 100BT (default).
52 NC unconnected Unused pin; no external connection.
53 NC unconnected Unused pin; no external connection.
54 VDDIO power_in 3.3V, 2.5V or 1.8V digital IO supply input; requires well-decoupled capacitors.
55 GND power_in Digital ground.
56 VDDCO power_out 1.8V core output from the internal LDO, supplying VDDA_1.8 and VDDC; do not connect an external supply.
57 NC unconnected Unused pin; no external connection.
58 P1LED1 bidirectional Port 1 LED indicator (speed by default); strap sets port 3 flow control (P3FFC), pull-up enables it.
59 P1LED0 bidirectional Port 1 LED indicator (link/activity by default); strap sets port 3 duplex (P3DPX), pull-up selects half-duplex; recommend external 0.5 kohm pull-down.
60 P2LED1 bidirectional Port 2 LED indicator (speed by default); with P2LED0 selects the serial bus configuration mode.
61 P2LED0 bidirectional Port 2 LED indicator (link/activity by default); with P2LED1 selects I2C master, I2C slave, SPI slave, or SMI/MIIM mode.
62 RSTN input Hardware reset input, active-low, with internal pull-up.
63 FXSD1 input MLL/RLL: connect to analog ground by pull-down resistor; FLL: fiber signal detect input.
64 VDDA_1.8 power_in 1.8V analog VDD input from VDDCO (pin 56) through an external ferrite bead and capacitors.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-64(10x10)
Category Communication Interface Chip/UART/485/232
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDDA_1.8, VDDC) 1.66 1.94 V 74
Supply Voltage (VDDA_3.3) 2.5 3.465 V 74
Supply Voltage (VDDIO) 1.71 3.465 V 74
Ambient Temperature (Commercial) TA 0 70 °C 74
Ambient Temperature (Industrial) TA -40 85 °C 74
Junction Temperature (TJ) TJ 125 °C 74
Supply Voltage (VDDA_1.8, VDDC) VIN -0.5 2.4 V 74
Supply Voltage (VDDA_3.3, VDDIO) VIN -0.5 4 V 74
Input Voltage VIN -0.5 4 V 74
Output Voltage -0.5 4 V 74
Lead Temperature (soldering, 10s) 260 °C soldering, 10s 74
Storage Temperature TS -55 150 °C 74
HBM ESD Rating -3 3 kV 74
Thermal Resistance LQFP (ΘJA) ΘJA 47.24 °C/W Note 5-1 No heat spreader (HS) in this package 74
Thermal Resistance LQFP (ΘJC) ΘJC 19.37 °C/W Note 5-1 No heat spreader (HS) in this package 74
CMOS Input High Voltage VIH 2 V VDDIO = 3.3V 75
CMOS Input High Voltage VIH 1.8 V VDDIO = 2.5V 75
CMOS Input High Voltage VIH 1.3 V VDDIO = 1.8V 75
CMOS Input Low Voltage VIL 0.8 V VDDIO = 3.3V 75
CMOS Input Low Voltage VIL 0.7 V VDDIO = 2.5V 75
CMOS Input Low Voltage VIL 0.5 V VDDIO = 1.8V 75
Input Current IIN -10 10 µA VIN = GND ~ VDDIO 75
CMOS Output High Voltage VOH 2.4 V IOH = -8 mA, VDDIO = 3.3V 75
CMOS Output High Voltage VOH 2 V IOH = -8 mA, VDDIO = 2.5V 75
CMOS Output High Voltage VOH 1.5 V IOH = -8 mA, VDDIO = 1.8V 75
CMOS Output Low Voltage VOL 0.4 V VIOL = 8 mA, VDDIO = 3.3V 75
CMOS Output Low Voltage VOL 0.3 V VIOL = 8 mA, VDDIO = 1.8V 75
Output Tri-State Leakage /IOZ/ 10 µA 75
Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination across differential output 75
Output Voltage Imbalance VIMB 2 % 100Ω termination across differential output 76
Rise/Fall Time tr/tf 3 5 ns 76
Rise/Fall Time Imbalance 0 0.5 ns 76
Duty Cycle Distortion -0.5 0.5 ns 76
Overshoot 5 % 76
Output Jitter (100BASE-TX) 0.7 1.4 ns Peak-to-peak 76
Output Jitter (10BASE-T) 1.4 11 ns Peak-to-peak 76
EEPROM Setup time ts1 20 ns 77
EEPROM Hold time th1 20 ns 77
EEPROM Output valid tov1 4096 4112 4128 ns 77

CAD (KiCad official)

  • Symbol: KSZ8873MLL
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ksz8873mll-etched.step / ksz8873mll-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8873mll.step / ksz8873mll.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (95 pp, sha256 5bfa1107d97e8afb, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF