KSZ8873FLLI from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RXM1	bidirectional	Port 1 physical receive or transmit signal (- differential).
2	RXP1	bidirectional	Port 1 physical receive or transmit signal (+ differential).
3	AGND	power_in	Analog ground.
4	TXM1	bidirectional	Port 1 physical transmit or receive signal (- differential).
5	TXP1	bidirectional	Port 1 physical transmit or receive signal (+ differential).
6	VDDA_3.3	power_in	3.3V analog VDD.
7	AGND	power_in	Analog ground.
8	ISET	output	Sets physical transmit output current; pull down with an 11.8kΩ 1% resistor to ground.
9	VDDA_1.8	power_in	1.8V analog core power input from VDDCO (pin 56).
10	RXM2	bidirectional	Port 2 physical receive or transmit signal (- differential).
11	RXP2	bidirectional	Port 2 physical receive or transmit signal (+ differential).
12	AGND	power_in	Analog ground.
13	TXM2	bidirectional	Port 2 physical transmit or receive signal (- differential).
14	TXP2	bidirectional	Port 2 physical transmit or receive signal (+ differential).
15	FXSD2	input	FLL: Port 2 fiber signal detect/factory test pin.
16	PWRDN	input	Chip power down input, active-low, with internal pull-up.
17	X1	input	25 MHz or 50 MHz crystal/oscillator clock connection (±50 ppm); with an oscillator, X1 connects to a 3.3V tolerant oscillator and clock should be applied before reset goes high.
18	X2	output	Crystal connection; no connect when an oscillator drives X1.
19	SMTXEN3	input	Switch MII transmit enable, internal pull-up.
20	SMTXD33/EN_REFCLKO_3	input	FLL: Switch MII transmit data bit 3, internal pull-up (EN_REFCLKO_3 strap applies to RLL only).
21	SMTXD32	input	FLL: Switch MII transmit data bit 2, internal pull-up.
22	SMTXD31	input	Switch MII/RMII transmit data bit 1, internal pull-up.
23	SMTXD30	input	Switch MII/RMII transmit data bit 0, internal pull-up.
24	GND	power_in	Digital ground.
25	VDDIO	power_in	3.3V, 2.5V, or 1.8V digital VDD input supply for IO with well decoupling capacitors.
26	SMTXC3/REFCLKI_3	bidirectional	FLL: Switch MII transmit clock; output in PHY MII mode and SNI mode, input in MAC MII mode.
27	SMTXER3/MII_LINK_3	input	Switch MII transmit error; in MII PHY mode 0 = MII link from host, 1 = no link on port 3 and enables bypass mode (internal pull-down).
28	SMRXDV3	bidirectional	Switch MII receive data valid; strap selects MII mode: PU = PHY mode, PD = MAC mode.
29	SMRXD33/REFCLKO_3	bidirectional	FLL: Switch MII receive data bit 3; strap enables auto-negotiation on port 2 (PU = enable, PD = disable).
30	SMRXD32	bidirectional	Switch MII receive data bit 2; strap forces port 2 speed if P2ANEN = 0 (PU = 100BT, PD = 10BT).
31	SMRXD31	bidirectional	Switch MII/RMII receive data bit 1; strap sets port 2 duplex (PU = full-duplex, PD = half-duplex).
32	GND	power_in	Digital ground.
33	SMRXD30	bidirectional	Switch MII/RMII receive data bit 0; strap forces port 2 flow control (PU = always enabled, PD = determined by auto-negotiation).
34	SCRS3/NC	bidirectional	FLL: Switch MII carrier sense; in MAC mode drive from PHY/FPGA CRS with logic (TXEN
35	SCOL3/NC	bidirectional	FLL: Switch MII collision detect.
36	SMRXC3/NC	bidirectional	FLL: Switch MII receive clock; output in PHY MII mode, input in MAC MII mode.
37	GND	power_in	Digital ground.
38	VDDC	power_in	1.8V digital core power input from VDDCO (pin 56).
39	SPIQ	bidirectional	SPI slave mode serial data output (external pull-up needed when in use); strap selects XCLK frequency: PU = 25 MHz, PD = 50 MHz.
40	SPISN	input	SPI slave mode chip select, active-low, internal pull-up; external pull-up needed when in use, high deselects and tri-states SPIQ.
41	INTRN	output	Active-low interrupt to host CPU indicating an interrupt status bit is set on lost link (registers 187 and 188), with internal pull-up.
42	SCL_MDC	bidirectional	SPI/I2C slave mode clock input, I2C master mode clock output, and MIIM clock input.
43	SDA_MDIO	bidirectional	SPI slave serial data input, I2C serial data input/output, and MIIM data input/output; external pull-up needed when in use.
44	NC	unconnected	Unused pin; only this NC pin may be pulled down by a resistor for better EMI.
45	P1ANEN	bidirectional	Strap: PU = enable auto-negotiation on port 1, PD = disable.
46	P1SPD	bidirectional	Strap: PU = force port 1 to 100BT, PD = 10BT, if P1ANEN = 0.
47	P1DPX	bidirectional	Strap: PU = port 1 full-duplex, PD = half-duplex (default or forced depending on P1ANEN).
48	GND	power_in	Digital ground.
49	VDDC	power_in	1.8V digital core power input from VDDCO (pin 56).
50	P1FFC	bidirectional	Strap: PU = always force port 1 flow control, PD = determined by auto-negotiation result.
51	P3SPD	bidirectional	Strap: PU = force port 3 to 10BT, PD = 100BT (default); internal pull-down.
52	NC	unconnected	Unused pin, no external connection.
53	NC	unconnected	Unused pin, no external connection.
54	VDDIO	power_in	3.3V, 2.5V or 1.8V digital VDD input supply for IO with well decoupling capacitors.
55	GND	power_in	Digital ground.
56	VDDCO	power_out	1.8V internal LDO regulator output (input from VDDIO) powering VDDA_1.8 and VDDC; do not connect an external supply, use ferrite bead between analog and digital 1.8V.
57	NC	unconnected	Unused pin, no external connection.
58	P1LED1	bidirectional	Port 1 LED (default speed, register 195 bit[5:4]); strap for port 3 flow control: PU = force enable (default), PD = disable.
59	P1LED0	bidirectional	Port 1 LED (default link/activity); strap for port 3 duplex: PU = half-duplex, PD = full-duplex (default); recommend external 0.5kΩ pull-down.
60	P2LED1	bidirectional	Port 2 LED (default speed); with P2LED0 straps serial bus mode: [P2LED1,P2LED0] 00 = I2C master, 01 = I2C slave, 10 = SPI slave, 11 = SMI/MIIM.
61	P2LED0	bidirectional	Port 2 LED (default link/activity); with P2LED1 straps serial bus configuration mode (00 I2C master, 01 I2C slave, 10 SPI slave, 11 SMI/MIIM).
62	RSTN	input	Hardware reset, active-low, with internal pull-up.
63	FXSD1	input	FLL: Port 1 fiber signal detect.
64	VDDA_1.8	power_in	1.8V analog VDD input supply from VDDCO (pin 56) through external ferrite bead and capacitors.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	LQFP-64(10x10)
Category	Communication Interface Chip/UART/485/232
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input High Voltage (VDDIO=3.3V)	VIH	2			V	VDDIO = 3.3V (printed 2.0/1.8/1.3 for 3.3/2.5/1.8V)	75
Input High Voltage (VDDIO=2.5V)	VIH	1.8			V	VDDIO = 2.5V	75
Input High Voltage (VDDIO=1.8V)	VIH	1.3			V	VDDIO = 1.8V	75
Input Low Voltage (VDDIO=3.3V)	VIL			0.8	V	VDDIO = 3.3V	75
Input Low Voltage (VDDIO=2.5V)	VIL			0.7	V	VDDIO = 2.5V	75
Input Low Voltage (VDDIO=1.8V)	VIL			0.5	V	VDDIO = 1.8V	75
Input Current	IIN	-10		10	µA	VIN = GND ~ VDDIO	75
Output High Voltage (VDDIO=3.3V)	VOH	2.4			V	IOH = -8 mA, VDDIO = 3.3V	75
Output High Voltage (VDDIO=2.5V)	VOH	2			V	IOH = -8 mA, VDDIO = 2.5V	75
Output High Voltage (VDDIO=1.8V)	VOH	1.5			V	IOH = -8 mA, VDDIO = 1.8V	75
Output Low Voltage (VDDIO=3.3V/2.5V)	VOL			0.4	V	IOL = 8 mA, VDDIO = 3.3V/2.5V	75
Output Low Voltage (VDDIO=1.8V)	VOL			0.3	V	IOL = 8 mA, VDDIO = 1.8V	75
Output Tri-State Leakage	/IOZ/			10	µA		75
Peak Differential Output Voltage (100BASE-TX)	VO	0.95		1.05	V	100Ω termination across differential output	75
Output Voltage Imbalance	VIMB			2	%	100Ω termination across differential output	76
Rise/Fall Time	tr/tf	3		5	ns		76
Rise/Fall Time Imbalance		0		0.5	ns		76
Duty Cycle Distortion		-0.5		0.5	ns		76
Overshoot				5	%		76
Output Jitter (100BASE-TX)			0.7	1.4	ns	Peak-to-peak	76
Output Jitter (10BASE-T)			1.4	11	ns	Peak-to-peak	76
100BASE-TX supply current, single supply	IDDXIO		115		mA	VDDA_3.3, VDDIO = 3.3V (single power); core from internal 1.8V LDO	75
100BASE-TX supply current, external 1.8V	IDD + IC		115		mA	VDDA_3.3, VDDIO = 3.3V; external 1.8V LDO (printed 32 + 83)	75
10BASE-T supply current, single supply	IDDXIO		85		mA	VDDA_3.3, VDDIO = 3.3V; core from internal LDO	75
Power Saving Mode current	IDD3		96		mA	VDDA_3.3, VDDIO = 3.3V; unplug port 1 and 2; Reg 195 bit[1,0]=[1,1]	75
Soft Power Down Mode current	IDD4		5		mA	VDDA_3.3, VDDIO = 3.3V; Reg 195 bit[1,0]=[1,0]	75
Energy Detect Mode current	IDD5		15		mA	VDDA_3.3, VDDIO = 3.3V; unplug port 1 and 2; Reg 195 bit[7,0]=0x05	75
Squelch Threshold	VSQ		400		mV	5 MHz square wave	76
10BASE-T Peak Differential Output Voltage	VP		2.4		V	100Ω termination across differential output	76
EEPROM Clock cycle	tcyc1		16384		ns		77
EEPROM Setup time	ts1	20			ns		77
EEPROM Hold time	th1	20			ns		77
EEPROM Output valid	tov1	4096	4112	4128	ns		77
Supply Voltage VDDA_1.8, VDDC (abs max)	VIN	-0.5		2.4	V		74
Supply Voltage VDDA_3.3, VDDIO (abs max)	VIN	-0.5		4	V		74
Input Voltage (abs max)		-0.5		4	V		74
Output Voltage (abs max)		-0.5		4	V		74
Lead Temperature				260	°C	soldering, 10s	74
Storage Temperature	TS	-55		150	°C		74
HBM ESD Rating		-3		3	kV		74
Supply Voltage VDDA_1.8, VDDC		1.66		1.94	V		74
Supply Voltage VDDA_3.3		2.5		3.465	V		74
Supply Voltage VDDIO		1.71		3.465	V		74
Ambient Temperature (Industrial)	TA	-40		85	°C	Industrial	74
Junction Temperature	TJ			125	°C		74
Thermal Resistance LQFP junction-to-ambient	ΘJA		47.24		°C/W	No heat spreader	74
Thermal Resistance LQFP junction-to-case	ΘJC		19.37		°C/W	No heat spreader	74

CAD (KiCad official)

Symbol: KSZ8873FLLI
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: ksz8873flli-etched.step / ksz8873flli-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8873flli.step / ksz8873flli.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (95 pp, sha256 5bfa1107d97e8afb, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

KSZ8873FLLI

Verified KSZ8873FLLI

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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