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KSZ8864CNXIA

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Microchip Tech Interface - Specialized, QFN-64-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ksz8864cnxiafactory-2.0.0extractor-text

Verified KSZ8864CNXIA

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: KSZ8864CNXIA · QFN-64-EP(8x8) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 98-page datasheet
  • ✓distributor: lcsc C633474, digikey KSZ8864CNXIA-ND, mouser 998-KSZ8864CNXIA
  • ✓family: QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-w3ebcbn3/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ksz8864cnxia.kicad_sym✓ ksz8864cnxia.kicad_mod✓ ksz8864cnxia.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7h ago
viewers ksz8864cnxia: viewers · Ray 7h ago
ksz8864cnxia-etched.glb Publish 0.1.0 · Ray 7h ago
ksz8864cnxia-etched.step ksz8864cnxia: factory component page (tier=mfr) · Ray 7h ago
ksz8864cnxia-hero.glb ksz8864cnxia: hero GLB from the etched model (keeps the MPN mark) · Ray 7h ago
ksz8864cnxia-hero.overlay.json Publish 0.1.0 · Ray 7h ago
ksz8864cnxia.glb Publish 0.1.0 · Ray 7h ago
ksz8864cnxia.kicad_mod Publish 0.1.0 · Ray 7h ago
ksz8864cnxia.kicad_sym Publish 0.1.0 · Ray 7h ago
ksz8864cnxia.lbr Publish 0.1.0 · Ray 7h ago
ksz8864cnxia.step Publish 0.1.0 · Ray 7h ago
package.json Publish 0.1.0 · Ray 7h ago
page.json Set visibility: public · Ray 7h ago
README.md Publish 0.1.0 · Ray 7h ago
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray 6h ago

KSZ8864CNXIA

Microchip Tech · Interface - Specialized · QFN-64-EP(8x8)

KSZ8864CNXIA from Microchip Tech, in a QFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXP1 input Port 1 physical receive signal + (differential).
2 RXM1 input Port 1 physical receive signal - (differential).
3 TXP1 output Port 1 physical transmit signal + (differential).
4 TXM1 output Port 1 physical transmit signal - (differential).
5 VDDA12 power_in 1.2V analog power.
6 GND power_in Ground, with all grounding of die bottom.
7 ISET passive Sets physical transmit output current; pull down with a 12.4 kΩ 1% resistor.
8 VDDAT power_in 3.3V analog VDD.
9 RXP2 input Port 2 physical receive signal + (differential).
10 RXM2 input Port 2 physical receive signal - (differential).
11 TXP2 output Port 2 physical transmit signal + (differential).
12 TXM2 output Port 2 physical transmit signal - (differential).
13 VDDAT power_in 3.3V analog VDD.
14 INTR_N output Interrupt, open-drain output with internal pull-up.
15 VDDC power_in 1.2V digital core VDD.
16 SM3TXEN input MAC3 switch MII/RMII transmit enable (internal pull-down).
17 SM3TXD3 input MAC3 switch MII transmit bit 3 (internal pull-down).
18 SM3TXD2 input MAC3 switch MII transmit bit 2 (internal pull-down).
19 SM3TXD1 input MAC3 switch MII/RMII transmit bit 1 (internal pull-down).
20 SM3TXD0 input MAC3 switch MII/RMII transmit bit 0 (internal pull-down).
21 SM3TXC/SM3REFCLK bidirectional MAC3 MII transmit clock: input in SW3-MII MAC mode, output in PHY mode, input as SW3-RMII reference clock.
22 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
23 SM3RXC bidirectional MAC3 MII receive clock: input in MAC mode, output in PHY mode, output as SW3-RMII reference clock; unused RMII clock can be pulled down or disabled by Register 87.
24 SM3RXDV/SM3CRSDV bidirectional SM3RXDV: MAC3 SW3-MII receive data valid; SM3CRSDV: SW3-RMII carrier sense/receive data valid (internal pull-down during reset).
25 SM3RXD3 bidirectional MAC3 MII receive bit 3; strap: PD (default) = enable flow control, PU = disable flow control.
26 SM3RXD2 bidirectional MAC3 MII receive bit 2; strap: PD (default) = disable back pressure, PU = enable back pressure.
27 SM3RXD1 bidirectional MAC3 MII/RMII receive bit 1; strap: PD (default) = drop excessive collision packets, PU = do not drop them.
28 SM3RXD0 bidirectional MAC3 MII/RMII receive bit 0; strap: PD (default) = disable aggressive back-off in half-duplex, PU = enable for performance enhancement.
29 SM3CRS bidirectional MAC3 switch MII carrier sense (internal pull-down during reset).
30 GND power_in Ground, with all grounding of die bottom.
31 SM3COL bidirectional MAC3 switch MII collision detect (internal pull-down during reset).
32 SM4TXEN input MAC4 switch MII/RMII transmit enable (internal pull-down).
33 SM4TXD3 input MAC4 switch MII transmit bit 3 (internal pull-down).
34 SM4TXD2 input MAC4 switch MII transmit bit 2 (internal pull-down).
35 SM4TXD1 input MAC4 switch MII/RMII transmit bit 1 (internal pull-down).
36 SM4TXD0 input MAC4 switch MII/RMII transmit bit 0 (internal pull-down).
37 SM4TXC/SM4REFCLK bidirectional MAC4 MII transmit clock: input in SW4-MII MAC mode, output in PHY mode, input as SW4-RMII reference clock (see strap P1LED1 for clock/normal mode).
38 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
39 SM4RXC bidirectional MAC4 MII receive clock: input in MAC mode, output in PHY mode, output 50 MHz SW4-RMII reference clock in clock mode (disable by Register 87 in normal mode).
40 SM4RXDV/SM4CRSDV bidirectional SM4RXDV: MAC4 SW4-MII receive data valid; SM4CRSDV: SW4-RMII carrier sense/receive data valid.
41 SM4RXD3 bidirectional MAC4 MII receive bit 3; strap: PD (default) = disable switch MII/RMII full-duplex flow control, PU = enable.
42 SM4RXD2 bidirectional MAC4 MII receive bit 2; strap: PD (default) = full-duplex, PU = half-duplex.
43 SM4RXD1 bidirectional MAC4 MII/RMII receive bit 1; strap: PD (default) = 100 Mbps mode, PU = 10 Mbps mode.
44 SM4RXD0 bidirectional MAC4 MII/RMII receive bit 0; strap LED mode: PD (default) = mode 0, PU = mode 1.
45 SM4COL bidirectional MAC4 MII collision detect: input in SW4-MII MAC mode, output in PHY mode.
46 SM4CRS bidirectional MAC4 MII carrier sense: input in SW4-MII MAC mode, output in PHY mode.
47 SCONF1 input With SCONF0 selects port 4 mode: 00 (default) PHY mode, 01 disable ports 3 and 4, 10 disable port 4 only, 11 MAC mode (internal pull-down).
48 SCONF0 input With SCONF1 selects port 4 SW4-MII PHY/MAC mode or port disable (internal pull-down); see pin 47.
49 P2LED1 bidirectional Port 2 LED indicator; must be pulled down by a 1 kΩ resistor in the design.
50 P2LED0 bidirectional Port 2 LED indicator; strap for MAC3: PU (default) = MII, PD = RMII.
51 P1LED1 bidirectional Port 1 LED indicator; strap for RMII: PU (default) = clock mode from 25 MHz crystal, PD = normal mode with external 50 MHz clock on SM4TXC.
52 P1LED0 bidirectional Port 1 LED indicator; strap for MAC4: PU (default) = MII, PD = RMII.
53 MDC input MII management (MIIM) or SMI interface clock (internal pull-up).
54 MDIO bidirectional MIIM management or SMI interface data I/O; needs an external pull-up when driven.
55 SPIQ bidirectional SPI serial data output in SPI slave mode; needs an external pull-up when driven.
56 SPIC/SCL bidirectional Input clock up to 25 MHz in SPI slave mode; output clock at 61 kHz in I2C master mode; needs an external pull-up when driven.
57 SPID/SDA bidirectional Serial data input in SPI slave mode; serial data input/output in I2C master mode; needs an external pull-up when driven.
58 SPIS_N input Active-low SPI slave select: high deselects device and tri-states SPIQ, high-to-low starts transfer; unused in I2C master mode.
59 PS1 input Serial bus configuration with PS0: 00 I2C master (EEPROM), 01 SMI, 10 SPI slave, 11 factory test (BIST).
60 PS0 input Serial bus configuration pin, used with PS1 (internal pull-down).
61 RST_N input Active-low device reset.
62 VDDC power_in 1.2V digital core VDD.
63 X1 input 25 MHz crystal connection or 3.3V oscillator input; tolerance ≤ ±50 ppm.
64 X2 output 25 MHz crystal clock connection.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(8x8)
Category Communication Interface Chip/UART/485/232
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog core supply voltage (VDDAR, VDDC) VDDAR, VDDC 1.14 1.26 V 78
Analog transmit supply voltage VDDAT 3.135 3.465 V 78
I/O supply voltage 3.3V VDDIO 3.135 3.465 V VDDIO @ 3.3V 78
I/O supply voltage 2.5V VDDIO 2.375 2.625 V VDDIO @ 2.5V 78
I/O supply voltage 1.8V VDDIO 1.71 1.89 V VDDIO @ 1.8V 78
Ambient temperature (Industrial) TA -40 85 °C TA Industrial 78
Maximum junction temperature TJ max 125 °C 78
Supply voltage (VDDAR, VDDC) absolute max VDDAR, VDDC -0.5 2.4 V 78
Supply voltage (VDDAT, VDDIO) absolute max VDDAT, VDDIO -0.5 4 V 78
Input voltage -0.5 4 V 78
Output voltage -0.5 4 V 78
Lead temperature 260 °C soldering, 10s 78
Storage temperature TS -55 150 °C 78
HBM ESD rating 5 kV 1.5 kΩ in series with 100 pF 78
Thermal resistance junction to ambient ΘJA 31.96 °C/W No heat spreader, air velocity 0 m/s 78
Thermal resistance junction to case ΘJC 13.54 °C/W No heat spreader, air velocity 0 m/s 78
Input high voltage (VDDIO=3.3/2.5/1.8V) VIH 2 V Printed 2.0/1.8/1.3 for VDDIO=3.3/2.5/1.8V; 3.3V value shown 79
Input low voltage (VDDIO=3.3/2.5/1.8V) VIL 0.8 V Printed 0.8/0.7/0.5 for VDDIO=3.3/2.5/1.8V; 3.3V value shown 79
Input current (excluding pull-up/pull-down) IIN -10 10 µA VIN = GND ~ VDDIO 79
Output high voltage (VDDIO=3.3/2.5/1.8V) VOH 2.4 V IOH = -8 mA; printed 2.4/2.0/1.5 for VDDIO=3.3/2.5/1.8V; 3.3V value shown 79
Output low voltage (VDDIO=3.3/2.5/1.8V) VOL 0.4 V IOL = 8 mA; printed 0.4/0.4/0.3 for VDDIO=3.3/2.5/1.8V; 3.3V value shown 80
Output tri-state leakage IOZ 10 µA VIN = GND ~ VDDIO 80
100BASE-TX peak differential output voltage VO 0.95 1.05 V 100Ω termination on the differential output 80
100BASE-TX output voltage imbalance VIMB 2 % 100Ω termination on the differential output 80
100BASE-TX rise/fall time tr/tf 3 5 ns 80
100BASE-TX rise/fall time imbalance 0 0.5 ns 80
100BASE-TX duty cycle distortion -0.5 0.5 ns printed ±0.5 80
100BASE-TX overshoot 5 % 80
100BASE-TX output jitter 0 0.75 1.4 ns Peak-to-Peak 80
10BASE-T receive squelch threshold VSQ 300 400 585 mV 5 MHz square wave 80
10BASE-T peak differential output voltage VP 2.2 2.5 2.8 V 100Ω termination on the differential output, VDDAT = 3.3V 80
10BASE-T output jitter 1.4 3.5 ns Peak-to-Peak 80
10BASE-T rise/fall times 28 30 ns 80
EEPROM setup time tS1 20 ns 81
EEPROM hold time tH1 20 ns 81
EEPROM output valid tOV1 4096 4112 4128 ns 81
EEPROM clock cycle tCYC1 16384 ns 81
100BASE-TX 3.3V analog current IDX 38 mA VDDAT, all ports 100% utilization 79
100BASE-TX 1.2V analog current IDda 13 mA VDDAR, all ports 100% utilization 79
100BASE-TX 1.2V digital current IDDc 41 mA VDDC, all ports 100% utilization 79
100BASE-TX 3.3V digital IO current IDDIO 27 mA VDDIO (SW3/4-MII/RMII) 79
10BASE-T 3.3V analog current IDX 48 mA VDDAT, all ports 100% utilization 79
10BASE-T 1.2V digital current IDDc 41 mA VDDC, all ports 100% utilization 79
Soft power-down 3.3V current ISPDM1 15 mA VDDAT + VDDIO 79
Soft power-down 1.2V current ISPDM2 1 mA VDDAR + VDDC 79

CAD (KiCad official)

  • Symbol: KSZ8864CNXIA
  • Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • 3D model: QFN-64-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: ksz8864cnxia-etched.step / ksz8864cnxia-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8864cnxia.step / ksz8864cnxia.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (98 pp, sha256 00c8886e1e293e06, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF