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KSZ8864CNXI

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Microchip Tech Ethernet ICs, QFN-64-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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KSZ8864CNXI

Microchip Tech · Ethernet ICs · QFN-64-EP(8x8)

KSZ8864CNXI from Microchip Tech, in a QFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXP1 input Physical receive signal + (differential) for the Port 1 PHY.
2 RXM1 input Physical receive signal - (differential) for the Port 1 PHY.
3 TXP1 output Physical transmit signal + (differential) for the Port 1 PHY.
4 TXM1 output Physical transmit signal - (differential) for the Port 1 PHY.
5 VDDA12 power_in 1.2V analog power supply.
6 GND power_in Ground, with all grounding of the die bottom.
7 ISET passive Sets the physical transmit output current; pull down with a 12.4 kΩ 1% resistor.
8 VDDAT power_in 3.3V analog VDD.
9 RXP2 input Physical receive signal + (differential) for the Port 2 PHY.
10 RXM2 input Physical receive signal - (differential) for the Port 2 PHY.
11 TXP2 output Physical transmit signal + (differential) for the Port 2 PHY.
12 TXM2 output Physical transmit signal - (differential) for the Port 2 PHY.
13 VDDAT power_in 3.3V analog VDD.
14 INTR_N output Interrupt output; this pin is an open-drain output.
15 VDDC power_in 1.2V digital core VDD.
16 SM3TXEN input MAC3 switch MII/RMII transmit enable; input with internal pull-down.
17 SM3TXD3 input MAC3 switch MII transmit bit 3; input with internal pull-down.
18 SM3TXD2 input MAC3 switch MII transmit bit 2; input with internal pull-down.
19 SM3TXD1 input MAC3 switch MII/RMII transmit bit 1; input with internal pull-down.
20 SM3TXD0 input MAC3 switch MII/RMII transmit bit 0; input with internal pull-down.
21 SM3TXC/SM3REFCLK bidirectional MAC3 MII transmit clock (input in MAC mode, output in PHY mode), or SW3-RMII reference clock input.
22 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
23 SM3RXC bidirectional MAC3 MII receive clock (input in MAC mode, output in PHY mode) or SW3-RMII reference clock output; an unused RMII clock can be pulled down or disabled by Register 87.
24 SM3RXDV/SM3CRSDV bidirectional SW3-MII receive data valid (SM3RXDV), or SW3-RMII carrier sense/receive data valid (SM3CRSDV); input with internal pull-down during reset.
25 SM3RXD3 bidirectional MAC3 MII receive bit 3; strap option: PD (default) enables flow control, PU disables flow control.
26 SM3RXD2 bidirectional MAC3 MII receive bit 2; strap option: PD (default) disables back pressure, PU enables back pressure.
27 SM3RXD1 bidirectional MAC3 MII/RMII receive bit 1; strap option: PD (default) drops excessive collision packets, PU does not drop them.
28 SM3RXD0 bidirectional MAC3 MII/RMII receive bit 0; strap option: PD (default) disables aggressive half-duplex back-off, PU enables it for performance.
29 SM3CRS bidirectional MAC3 switch MII carrier sense.
30 GND power_in Ground, with all grounding of the die bottom.
31 SM3COL bidirectional MAC3 switch MII collision detect.
32 SM4TXEN input MAC4 switch MII/RMII transmit enable; input with internal pull-down.
33 SM4TXD3 input MAC4 switch MII transmit bit 3; input with internal pull-down.
34 SM4TXD2 input MAC4 switch MII transmit bit 2; input with internal pull-down.
35 SM4TXD1 input MAC4 switch MII/RMII transmit bit 1; input with internal pull-down.
36 SM4TXD0 input MAC4 switch MII/RMII transmit bit 0; input with internal pull-down.
37 SM4TXC/SM4REFCLK bidirectional MAC4 MII transmit clock (input in SW4-MII MAC mode, output in SW4-MII PHY mode), or SW4-RMII reference clock input selected by the P1LED1 strap.
38 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
39 SM4RXC bidirectional MAC4 MII receive clock (input in MAC mode, output in PHY mode) or SW4-RMII 50 MHz reference clock output in default clock mode; disable by Register 87 in normal mode.
40 SM4RXDV/SM4CRSDV bidirectional SW4-MII receive data valid (SM4RXDV), or SW4-RMII carrier sense/receive data valid (SM4CRSDV); input with internal pull-down during reset.
41 SM4RXD3 bidirectional MAC4 MII receive bit 3; strap option: PD (default) disables switch MII/RMII full-duplex flow control, PU enables it.
42 SM4RXD2 bidirectional MAC4 MII receive bit 2; strap option: PD (default) selects full-duplex mode, PU selects half-duplex mode.
43 SM4RXD1 bidirectional MAC4 MII/RMII receive bit 1; strap option: PD (default) selects 100 Mbps mode, PU selects 10 Mbps mode.
44 SM4RXD0 bidirectional MAC4 MII/RMII receive bit 0; strap option for LED mode: PD (default) mode 0, PU mode 1.
45 SM4COL bidirectional MAC4 switch MII collision detect (input in MAC modes, output in PHY modes).
46 SM4CRS bidirectional MAC4 switch MII carrier sense (input in MAC modes, output in PHY modes).
47 SCONF1 input Port 4 MAC4 MII mode select together with SCONF0: 00 (default) PHY mode, 01 disables port 3 and port 4, 10 disables port 4 only, 11 MAC mode; input with internal pull-down.
48 SCONF0 input Port 4 MAC4 MII mode select together with SCONF1 (see pin 47); input with internal pull-down.
49 P2LED1 bidirectional LED indicator for Port 2; this pin must be pulled down by a 1 kΩ resistor in this design.
50 P2LED0 bidirectional LED indicator for Port 2; strap option for Switch MAC3: PU (default) selects SW3-MII, PD selects SW3-RMII.
51 P1LED1 bidirectional LED indicator for Port 1; strap option for RMII: PU (default) clock mode with 25 MHz crystal on X1/X2, PD normal mode with external 50 MHz clock on SM4TXC.
52 P1LED0 bidirectional LED indicator for Port 1; strap option for Switch MAC4: PU (default) selects SW4-MII, PD selects SW4-RMII.
53 MDC input MIIM management interface clock, or SMI interface clock; input with internal pull-up.
54 MDIO bidirectional MIIM management data I/O, or SMI interface data I/O; needs an external pull-up when driven.
55 SPIQ bidirectional SPI serial data output in SPI slave mode; needs an external pull-up when driven.
56 SPIC/SCL bidirectional SPI slave clock input up to 25 MHz, or output clock at 61 kHz in I2C master mode; needs an external pull-up when driven.
57 SPID/SDA bidirectional Serial data input in SPI slave mode, or serial data input/output in I2C master mode; needs an external pull-up when driven.
58 SPIS_N input Active-low SPI slave select: when high the device is deselected and SPIQ is high-impedance; not used in I2C master mode.
59 PS1 input Serial bus configuration pin with PS0: 00 I2C master for EEPROM, 01 SMI, 10 SPI slave, 11 factory test (BIST); defaults to 00 if no EEPROM is present.
60 PS0 input Serial bus configuration pin (with PS1, see pin 59); input with internal pull-down.
61 RST_N input Active-low device reset; input with internal pull-up.
62 VDDC power_in 1.2V digital core VDD.
63 X1 input 25 MHz crystal connection or 3.3V oscillator input; crystal/oscillator tolerance must be ≤ ±50 ppm.
64 X2 output 25 MHz crystal connection.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(8x8)
Category Communication Interface Chip/UART/485/232
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDDAR, VDDC) VDDAR, VDDC -0.5 2.4 V 78
Supply Voltage (VDDAT, VDDIO) VDDAT, VDDIO -0.5 4 V 78
Input Voltage -0.5 4 V 78
Output Voltage -0.5 4 V 78
Lead Temperature (soldering, 10s) 260 °C soldering, 10s 78
Storage Temperature TS -55 150 °C 78
HBM ESD Rating 5 kV Human body model, 1.5 kΩ in series with 100 pF 78
Supply Voltage (VDDAR, VDDC) VDDAR, VDDC 1.14 1.26 V 78
Supply Voltage (VDDAT) VDDAT 3.135 3.465 V 78
Supply Voltage (VDDIO @ 3.3V) VDDIO 3.135 3.465 V VDDIO @ 3.3V 78
Supply Voltage (VDDIO @ 2.5V) VDDIO 2.375 2.625 V VDDIO @ 2.5V 78
Supply Voltage (VDDIO @ 1.8V) VDDIO 1.71 1.89 V VDDIO @ 1.8V 78
Ambient Temperature (TA Industrial) TA -40 85 °C TA Industrial 78
Maximum Junction Temperature (TJ max.) TJ 125 °C 78
Input High Voltage VIH 2 V VDDIO = 3.3V 79
Input High Voltage VIH 1.8 V VDDIO = 2.5V 79
Input High Voltage VIH 1.3 V VDDIO = 1.8V 79
Input Low Voltage VIL 0.8 V VDDIO = 3.3V 79
Input Low Voltage VIL 0.7 V VDDIO = 2.5V 79
Input Low Voltage VIL 0.5 V VDDIO = 1.8V 79
Input Current (Excluding Pull-Up/Pull-Down) IIN -10 10 µA VIN = GND ~ VDDIO 79
Input High Voltage (CMOS Outputs, as printed) VOH 2.4 V VDDIO = 3.3V; IOH = -8 mA 79
Input High Voltage (CMOS Outputs, as printed) VOH 2 V VDDIO = 2.5V; IOH = -8 mA 79
Input High Voltage (CMOS Outputs, as printed) VOH 1.5 V VDDIO = 1.8V; IOH = -8 mA 79
Input Low Voltage (CMOS Outputs, as printed) VOL 0.4 V VDDIO = 3.3V; VIOL = 8 mA 80
Input Low Voltage (CMOS Outputs, as printed) VOL 0.3 V VDDIO = 1.8V; VIOL = 8 mA 80
Output Tri-State Leakage IOZ 10 µA VIN = GND ~ VDDIO 80
100BASE-TX Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination on the differential output 80
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination on the differential output 80
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 80
100BASE-TX Rise/Fall Time Imbalance 0 0.5 ns 80
100BASE-TX Duty Cycle Distortion -0.5 0.5 ns 80
100BASE-TX Overshoot 5 % 80
10BASE-T Receive Squelch Threshold VSQ 300 400 585 mV 5 MHz square wave 80
10BASE-T Peak Differential Output Voltage VP 2.2 2.5 2.8 V VDDAT = 3.3V; 100Ω termination on the differential output 80
Thermal Resistance (ΘJA) ΘJA 31.96 °C/W No heat spreader in package; air velocity 0 m/s 78
Thermal Resistance (ΘJC) ΘJC 13.54 °C/W No heat spreader in package; air velocity 0 m/s 78

CAD (KiCad official)

  • Symbol: KSZ8864CNXI
  • Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • 3D model: QFN-64-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: ksz8864cnxi-etched.step / ksz8864cnxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8864cnxi.step / ksz8864cnxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (98 pp, sha256 00c8886e1e293e06, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF