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KSZ8863MLLI

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Microchip Tech Ethernet ICs, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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KSZ8863MLLI

Microchip Tech · Ethernet ICs · LQFP-48(7x7)

KSZ8863MLLI from Microchip Tech, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXM1 bidirectional Port 1 physical receive or transmit signal, negative differential.
2 RXP1 bidirectional Port 1 physical receive or transmit signal, positive differential.
3 TXM1 bidirectional Port 1 physical transmit or receive signal, negative differential.
4 TXP1 bidirectional Port 1 physical transmit or receive signal, positive differential.
5 VDDA_3.3 power_in 3.3V analog VDD supply.
6 ISET output Sets physical transmit output current; pull down to ground with an 11.8 kΩ 1% resistor.
7 VDDA_1.8 power_in 1.8V analog core power input, supplied from VDDCO (pin 42).
8 RXM2 bidirectional Port 2 physical receive or transmit signal, negative differential.
9 RXP2 bidirectional Port 2 physical receive or transmit signal, positive differential.
10 AGND power_in Analog ground.
11 TXM2 bidirectional Port 2 physical transmit or receive signal, negative differential.
12 TXP2 bidirectional Port 2 physical transmit or receive signal, positive differential.
13 NC unconnected No connection.
14 X1 input 25 MHz or 50 MHz crystal or oscillator clock input (±50 ppm); with an oscillator, X1 connects to a 3.3V tolerant oscillator, and the clock should be applied before reset goes high.
15 X2 output Crystal connection for the 25/50 MHz clock; no connect when an oscillator drives X1.
16 SMTXEN3 input Switch MII transmit enable, with internal pull-up.
17 SMTXD33/EN_REFCLKO_3 input On MLL, switch MII transmit data bit 3 (EN_REFCLKO_3 strap applies to RLL only), with internal pull-up.
18 SMTXD32 input Switch MII transmit data bit 2, with internal pull-up.
19 SMTXD31 input Switch MII transmit data bit 1, with internal pull-up.
20 SMTXD30 input Switch MII transmit data bit 0, with internal pull-up.
21 GND power_in Digital ground.
22 VDDIO power_in 3.3V, 2.5V, or 1.8V digital IO supply input, to be well decoupled.
23 SMTXC3/REFCLKI_3 bidirectional On MLL, switch MII transmit clock: output in PHY MII mode and SNI mode, input in MAC MII mode.
24 SMTXER3/MII_LINK_3 input Switch port 3 MII transmit error; in MII PHY mode 0 = link indicator from host, 1 = no link on port 3 and enables bypass mode; internal pull-down.
25 SMRXDV3 bidirectional Switch MII receive data valid; strap option for port 1 duplex (P1DPX): PU = full-duplex, PD = half-duplex.
26 SMRXD33/REFCLKO_3 bidirectional On MLL, switch MII receive data bit 3; strap option to enable auto-negotiation on port 2 (P2ANEN), PU = enable, PD = disable.
27 SMRXD32 bidirectional Switch MII receive data bit 2; strap option for port 2 speed (P2SPD), PU = 100BT, PD = 10BT when P2ANEN = 0.
28 SMRXD31 bidirectional Switch MII receive data bit 1; strap option for port 2 duplex (P2DPX), PU = full-duplex, PD = half-duplex.
29 SMRXD30 bidirectional Switch MII receive data bit 0; strap option for port 2 forced flow control (P2FFC), PU = always enabled, PD = determined by auto-negotiation.
30 SMRXC3 bidirectional Switch MII receive clock: output in PHY MII mode, input in MAC MII mode.
31 GND power_in Digital ground.
32 VDDC power_in 1.8V digital core power input, supplied from VDDCO (pin 42).
33 SCOL3 bidirectional Switch MII collision detect; input with internal pull-up during reset, output otherwise.
34 SCRS3 bidirectional Switch MII carrier sense; input with internal pull-up during reset, output otherwise.
35 INTRN output Active-low interrupt to host CPU indicating an interrupt status bit is set on lost link (registers 187 and 188); internal pull-up.
36 SCL_MDC bidirectional Clock for SPI slave/I2C slave (input), I2C master (output) and MIIM (input).
37 SDA_MDIO bidirectional Serial data: SPI slave data input, I2C data input/output, or MIIM data input/output; external pull-up needed when in use.
38 SPIQ bidirectional SPI slave serial data output (external pull-up needed when in use); strap option for port 1 forced flow control (P1FFC), PU = always enabled, PD = by auto-negotiation.
39 SPISN input SPI slave chip select, active-low; high deselects the device and tri-states SPIQ; external pull-up needed when using SPI or MDC/MDIO mode.
40 VDDIO power_in 3.3V, 2.5V, or 1.8V digital IO supply input, to be well decoupled.
41 GND power_in Digital ground.
42 VDDCO power_out 1.8V internal LDO regulator output powering VDDA_1.8 and VDDC; do not connect an external supply, and a ferrite bead is requested between analog and digital 1.8V.
43 P1LED1 bidirectional Port 1 LED indicator (default speed); strap option for port 1 speed (P1SPD), PU = 100BT, PD = 10BT when P1ANEN = 0.
44 P1LED0 bidirectional Port 1 LED indicator (default link/activity); strap option to enable port 1 auto-negotiation (P1ANEN), PU = enable, PD = disable (default).
45 P2LED1 bidirectional Port 2 LED indicator (default speed); with P2LED0 straps serial bus mode: [0,0] I2C master, [0,1] I2C slave, [1,0] SPI slave, [1,1] SMI/MIIM.
46 P2LED0 bidirectional Port 2 LED indicator (default link/activity); with P2LED1 straps serial bus configuration mode.
47 RSTN input Hardware reset, active-low, with internal pull-up.
48 FXSD1 input Fiber signal detect on FLL; on MLL no connection or connect to analog ground through a 1 kΩ pull-down resistor.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-48(7x7)
Category Interface ICs
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDDA_1.8, VDDC (abs max) VIN -0.5 2.4 V VDDA_1.8, VDDC 71
Supply Voltage VDDA_3.3, VDDIO (abs max) VIN -0.5 4 V VDDA_3.3, VDDIO 71
Input Voltage -0.5 4 V 71
Output Voltage -0.5 4 V 71
Lead Temperature 260 °C soldering, 10s 71
Storage Temperature TS -55 150 °C 71
HBM ESD Rating 4 kV 71
Operating Supply Voltage VDDA_1.8, VDDC 1.67 1.94 V VDDA_1.8, VDDC 71
Operating Supply Voltage VDDA_3.3 3.135 3.465 V VDDA_3.3 71
Operating Supply Voltage VDDIO 1.71 3.465 V VDDIO 71
Ambient Temperature (Industrial) TA -40 85 °C Industrial 71
Junction Temperature TJ 125 °C 71
Thermal Resistance LQFP junction-to-ambient ΘJA 52.83 °C/W No heat spreader 71
Thermal Resistance LQFP junction-to-case ΘJC 19.12 °C/W No heat spreader 71
Input High Voltage VIH 2 V VDDIO = 3.3V (min printed 2.0/1.8/1.3 for 3.3/2.5/1.8V) 72
Input Low Voltage VIL 0.8 V VDDIO = 3.3V (max printed 0.8/0.7/0.5 for 3.3/2.5/1.8V) 72
Input Current IIN -10 10 µA VIN = GND ~ VDDIO 72
Output High Voltage VOH 2.4 V IOH = 8 mA, VDDIO = 3.3V (min printed 2.4/2.0/1.5 for 3.3/2.5/1.8V) 72
Output Low Voltage VOL 0.4 V IOL = 8 mA, VDDIO = 3.3V (max printed 0.4/0.4/0.3 for 3.3/2.5/1.8V) 72
Output Tri-State Leakage /IOZ/ 10 µA 72
100BASE-TX Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination across differential output 72
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination across differential output 72
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 72
100BASE-TX Rise/Fall Time Imbalance 0 0.5 ns 72
100BASE-TX Duty Cycle Distortion -0.5 0.5 ns 72
100BASE-TX Overshoot 5 % 72
100BASE-TX Output Jitter 0.7 1.4 ns Peak-to-peak 72
10BASE-T Transmit Output Jitter 1.4 11 ns Peak-to-peak 73
100BASE-TX supply current IDDXIO 114 mA VDDA_3.3, VDDIO = 3.3V; all ports 100% utilization 72
10BASE-T supply current IDDXIO 85 mA VDDA_3.3, VDDIO = 3.3V; all ports 100% utilization 72
Power Saving Mode current IDD3 96 mA VDDA_3.3, VDDIO = 3.3V; Unplug Port 1 and Port 2; Register 195 bit[1,0] = [1,1] 72
Soft Power Down Mode current IDD4 8 mA VDDA_3.3, VDDIO = 3.3V; Register 195 bit[1,0] = [1,0] 72
Energy Detect Mode current IDD5 16 mA VDDA_3.3, VDDIO = 3.3V; Unplug Port 1 and Port 2 72
10BASE-T Squelch Threshold VSQ 400 mV 5 MHz square wave 73
10BASE-T Peak Differential Output Voltage VP 2.4 V 100Ω termination across differential output 73
EEPROM Setup time ts1 20 ns 74
EEPROM Hold time th1 20 ns 74
EEPROM Output valid tov1 4096 4112 4128 ns 74
EEPROM Clock cycle tcyc1 16384 ns 74

CAD (KiCad official)

  • Symbol: KSZ8863MLLI
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ksz8863mlli-etched.step / ksz8863mlli-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8863mlli.step / ksz8863mlli.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (92 pp, sha256 630e943d040b893a, retrieved 2026-10-27, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF