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Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

KSZ8851-16MLLI

Microchip Tech · Ethernet Controllers · LQFP-48(7x7)

KSZ8851-16MLLI from Microchip Tech, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P1LED1	output	Programmable LED output indicating port activity or 100 Mbps speed (LED ON=LOW), used for 16-/8-bit bus mode selection during power-up/reset where no connect or pull-up selects 16-bit mode and pull-down selects 8-bit mode.
2	P1LED0	output	Programmable LED output indicating link status or link/activity (LED ON=LOW) per Chip Global Control Register CGCR bit 9 setting.
3	PME	output	Power Management Event output (active low or high per PMECR[12]) asserted when wake-on-LAN events are detected (energy, linkup, magic packet, or wake-up frame).
4	INTRN	output	Interrupt output (active low) to host CPU requiring external 4.7 kΩ pull-up resistor when an interrupt status bit is set.
5	RDN	input	Asynchronous read strobe input (active low) indicating a read cycle with data valid 24-32 ns after RDN activation.
6	WRN	input	Asynchronous write strobe input (active low) indicating a write cycle requiring minimum 40 ns active time.
7	DGND	power_in	Digital ground reference.
8	VDD_CO1.8	power_out	1.8V regulator output providing power to VDD_A1.8 and VDD_D1.8 pins or left floating if external 1.8V supply is tied to VDD_IO pins.
9	EED_IO	bidirectional	EEPROM serial data I/O line for external EEPROM communication with internal pull-down during power-up/reset, latched to indicate EEPROM presence (pull-up=present, no connect/pull-down=absent).
10	EESK	output	EEPROM serial clock output (4 μs or 800 ns cycle at 25 MHz or 125 MHz respectively) with internal pull-down during power-up/reset, latched for endian mode selection (pull-up=big endian, no connect/pull-down=little endian).
11	CMD	input	Command type input selecting shared data bus access where low selects data access and high selects address/byte-enable access.
12	CSN	input	Chip select input (active low) enabling shared data bus access for read or write operations.
13	AGND	power_in	Analog ground reference.
14	VDD_A1.8	power_in	1.8V analog power supply from VDD_CO1.8 or external source (if VDD_IO=1.8V) requiring appropriate filtering capacitors.
15	EECS	output	EEPROM chip select output (active low) for selecting external EEPROM device during serial communication.
16	RXP1	input	Port 1 differential receive signal (positive input) from isolation transformer for 10BASE-T/100BASE-TX physical layer.
17	RXM1	input	Port 1 differential receive signal (negative input) from isolation transformer for 10BASE-T/100BASE-TX physical layer.
18	AGND	power_in	Analog ground reference.
19	TXP1	output	Port 1 differential transmit signal (positive output) to isolation transformer with ±0.95V to ±1.05V peak differential voltage at 100Ω termination.
20	TXM1	output	Port 1 differential transmit signal (negative output) to isolation transformer with ±0.95V to ±1.05V peak differential voltage at 100Ω termination.
21	VDD_A3.3	power_in	3.3V analog power supply input requiring appropriate decoupling capacitors.
22	ISET	output	Transmit output current setting pin pulled to ground with 3.01 kΩ 1% resistor to set MAU current level.
23	RSTN	input	Hardware reset input (active low) requiring minimum 10 ms low pulse after stable 3.3V supply voltage for proper device initialization.
24	X1	input	25 MHz crystal or 3.3V oscillator input (±50 ppm tolerance required) for system clock generation.
25	X2	output	25 MHz crystal output connection or no-connect if external oscillator is used for X1.
26	DGND	power_in	Digital ground reference.
27	VDD_IO	power_in	3.3V, 2.5V, or 1.8V digital I/O power supply input for CPU interface logic requiring appropriate decoupling capacitors.
28	DGND	power_in	Digital ground reference.
29	VDD_D1.8	power_in	1.8V digital core power supply from VDD_CO1.8 or external source (if VDD_IO=1.8V) requiring appropriate filtering.
30	SD15	bidirectional	Shared data bus bit 15 for data access when CMD=0; byte enable 3 (BE3, 4th byte enable, active high) when CMD=1 in 16-bit mode; must be tied to GND in 8-bit mode.
31	SD14	bidirectional	Shared data bus bit 14 for data access when CMD=0; byte enable 2 (BE2, 3rd byte enable, active high) when CMD=1 in 16-bit mode; must be tied to GND in 8-bit mode.
32	SD13	bidirectional	Shared data bus bit 13 for data access when CMD=0; byte enable 1 (BE1, 2nd byte enable, active high) when CMD=1 in 16-bit mode; must be tied to GND in 8-bit mode.
33	SD12	bidirectional	Shared data bus bit 12 for data access when CMD=0; byte enable 0 (BE0, 1st byte enable, active high) when CMD=1 in 16-bit mode; must be tied to GND in 8-bit mode.
34	SD11	bidirectional	Shared data bus bit 11 for data D11 access when CMD=0, do-not-care when CMD=1 in 16-bit mode; must be tied to GND in 8-bit mode.
35	SD10	bidirectional	Shared data bus bit 10 for data D10 access when CMD=0, do-not-care when CMD=1 in 16-bit mode; must be tied to GND in 8-bit mode.
36	SD9	bidirectional	Shared data bus bit 9 for data D9 access when CMD=0, do-not-care when CMD=1 in 16-bit mode; must be tied to GND in 8-bit mode.
37	DGND	power_in	Digital ground reference.
38	VDD_IO	power_in	3.3V, 2.5V, or 1.8V digital I/O power supply input for CPU interface logic requiring appropriate decoupling capacitors.
39	SD8	bidirectional	Shared data bus bit 8 for data D8 access when CMD=0, do-not-care when CMD=1; must be tied to GND in 8-bit mode.
40	SD7	bidirectional	Shared data bus bit 7 for data D7 access when CMD=0, address A7 access when CMD=1 in both 8-bit and 16-bit modes.
41	SD6	bidirectional	Shared data bus bit 6 for data D6 access when CMD=0, address A6 access when CMD=1 in both 8-bit and 16-bit modes.
42	SD5	bidirectional	Shared data bus bit 5 for data D5 access when CMD=0, address A5 access when CMD=1 in both 8-bit and 16-bit modes.
43	SD4	bidirectional	Shared data bus bit 4 for data D4 access when CMD=0, address A4 access when CMD=1 in both 8-bit and 16-bit modes.
44	SD3	bidirectional	Shared data bus bit 3 for data D3 access when CMD=0, address A3 access when CMD=1 in both 8-bit and 16-bit modes.
45	SD2	bidirectional	Shared data bus bit 2 for data D2 access when CMD=0, address A2 access when CMD=1 in both 8-bit and 16-bit modes.
46	VDD_IO	power_in	3.3V, 2.5V, or 1.8V digital I/O power supply input for CPU interface logic requiring appropriate decoupling capacitors.
47	SD1	bidirectional	Shared data bus bit 1 for data D1 access when CMD=0; address A1 access when CMD=1 in 8-bit mode, do-not-care when CMD=1 in 16-bit mode.
48	SD0	bidirectional	Shared data bus bit 0 for data D0 access when CMD=0; address A0 access when CMD=1 in 8-bit mode, do-not-care when CMD=1 in 16-bit mode.

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	LQFP-48(7x7)
Category	Interface
Pins	48

CAD (KiCad official)

Symbol: KSZ8851-16MLLI
Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
3D model files: ksz8851-16mlli-etched.step / ksz8851-16mlli-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8851-16mlli.step / ksz8851-16mlli.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (85 pp, sha256 48923de9b6d88788, retrieved 2026-09-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF