component

KSZ8795CLXIC

Public Made by Adom

by adom

Microchip Tech Ethernet ICs, LQFP-80(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsksz8795clxicfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers ksz8795clxic: symbol viewer · Ray 5d ago
ksz8795clxic-etched.glb Publish 0.1.0 · Ray 17d ago
ksz8795clxic-etched.step ksz8795clxic: factory component page (tier=mfr) · Ray 17d ago
ksz8795clxic-hero.glb ksz8795clxic: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
ksz8795clxic-hero.overlay.json Publish 0.1.0 · Ray 17d ago
ksz8795clxic.glb Publish 0.1.0 · Ray 17d ago
ksz8795clxic.kicad_mod Publish 0.1.0 · Ray 17d ago
ksz8795clxic.kicad_sym ksz8795clxic: symbol repaired (body fitted to the names) · Ray 5d ago
ksz8795clxic.lbr ksz8795clxic: symbol repaired (body fitted to the names) · Ray 5d ago
ksz8795clxic.step Publish 0.1.0 · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago

KSZ8795CLXIC

Microchip Tech · Ethernet ICs · LQFP-80(10x10)

KSZ8795CLXIC from Microchip Tech, in a LQFP-80(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD12A power_in 1.2V core power.
2 VDDAT power_in 3.3V or 2.5V analog power.
3 GNDA power_in Analog ground.
4 RXP1 input Port 1 physical receive signal + (differential).
5 RXM1 input Port 1 physical receive signal - (differential).
6 TXP1 output Port 1 physical transmit signal + (differential).
7 TXM1 output Port 1 physical transmit signal - (differential).
8 RXP2 input Port 2 physical receive signal + (differential).
9 RXM2 input Port 2 physical receive signal - (differential).
10 TXP2 output Port 2 physical transmit signal + (differential).
11 TXM2 output Port 2 physical transmit signal - (differential).
12 VDDAT power_in 3.3V or 2.5V analog power.
13 RXP3 input Port 3 physical receive signal + (differential).
14 RXM3 input Port 3 physical receive signal - (differential).
15 TXP3 output Port 3 physical transmit signal + (differential).
16 TXM3 output Port 3 physical transmit signal - (differential).
17 RXP4 input Port 4 physical receive signal + (differential).
18 RXM4 input Port 4 physical receive signal - (differential).
19 TXP4 output Port 4 physical transmit signal + (differential).
20 TXM4 output Port 4 physical transmit signal - (differential).
21 GNDA power_in Analog ground.
22 NC unconnected No connect.
23 INTR_N output Active-low open-drain interrupt output; needs an external pull-up resistor when in use.
24 LED3_1 bidirectional Port 3 LED indicator 1 (input with pull-up during reset); strap selects Port 5 GMAC5 mode with LED3_0: 00 MII, 01 RMII, 10 GMII, 11 RGMII (default).
25 LED3_0 bidirectional Port 3 LED indicator 0 (input with pull-up during reset); strap bit with LED3_1 for Port 5 GMAC5 interface mode select.
26 VDD12D power_in 1.2V core power.
27 GNDD power_in Digital ground.
28 LED4_1 bidirectional Port 4 LED indicator 1 (input with pull-up during reset, output otherwise).
29 TXEN5/TXD5_CTL input Port 5 transmit enable in GMII/MII/RMII; transmit data control in RGMII (internal pull-down).
30 TXD5_0 input Port 5 switch transmit bit 0 in GMII/RGMII/MII/RMII (internal pull-down).
31 LED4_0 bidirectional Port 4 LED indicator 0 (input with pull-up during reset, output otherwise).
32 TXD5_1 input Port 5 switch transmit bit 1 in GMII/RGMII/MII/RMII (internal pull-down).
33 GNDD power_in Digital ground.
34 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
35 TXD5_2 input Port 5 switch transmit bit 2 in GMII/RGMII/MII; no connection in RMII.
36 TXD5_3 input Port 5 switch transmit bit 3 in GMII/RGMII/MII; no connection in RMII.
37 TXER5 input Port 5 switch transmit error in GMII/MII; no connection in RGMII/RMII.
38 TXD5_4 input Port 5 switch transmit bit 4 in GMII; no connection in RGMII/MII/RMII.
39 TXD5_5 input Port 5 switch transmit bit 5 in GMII; no connection in RGMII/MII/RMII.
40 TXD5_6 input Port 5 switch transmit bit 6 in GMII; no connection in RGMII/MII/RMII.
41 TXD5_7 input Port 5 switch transmit bit 7 in GMII; no connection in RGMII/MII/RMII.
42 VDD12D power_in 1.2V core power.
43 TXC5/REFCLKI/GTXC5 bidirectional Port 5 GMAC5 clock: MII 2.5/25 MHz (output in PHY mode, input in MAC mode), RMII 50 MHz input, GMII/RGMII 125 MHz transmit clock input.
44 RXC5/GRXC5 bidirectional Port 5 GMAC5 clock: MII 2.5/25 MHz (output in PHY mode, input in MAC mode), RMII 50 MHz reference output, GMII/RGMII 125 MHz receive clock output.
45 RXD5_0 bidirectional Port 5 switch receive bit 0 in GMII/RGMII/MII/RMII (pull-down input during reset, output otherwise).
46 RXD5_1 bidirectional Port 5 switch receive bit 1 in GMII/RGMII/MII/RMII (pull-down input during reset, output otherwise).
47 GNDD power_in Digital ground.
48 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
49 RXD5_2 bidirectional Port 5 switch receive bit 2 in GMII/RGMII/MII; no connection in RMII.
50 RXD5_3 bidirectional Port 5 switch receive bit 3 in GMII/RGMII/MII; no connection in RMII.
51 RXDV5/CRSDV5/RXD5_CTL bidirectional Port 5 receive data valid (GMII/MII), carrier sense/receive data valid (RMII), or receive data control (RGMII).
52 RXER5 bidirectional Port 5 switch receive error in GMII/MII; no connection in RGMII/RMII.
53 CRS5 bidirectional Port 5 carrier sense in GMII/MII; no connection in RGMII/RMII.
54 COL5 bidirectional Port 5 collision detect in GMII/MII; no connection in RGMII/RMII.
55 REFCLKO bidirectional 25 MHz clock output option, controlled by strap pin LED2_0 and Global Register 11 bit 1; enabled by default, better disabled if unused.
56 PME_N bidirectional Power management event signal indicating a Wake-on-LAN event; polarity programmable, default active-low.
57 RXD5_4 bidirectional Port 5 switch receive bit 4 in GMII; no connection in RGMII/MII/RMII.
58 RXD5_5 bidirectional Port 5 switch receive bit 5 in GMII; no connection in RGMII/MII/RMII.
59 RXD5_6 bidirectional Port 5 switch receive bit 6 in GMII; no connection in RGMII/MII/RMII.
60 RXD5_7 bidirectional Port 5 switch receive bit 7 in GMII; no connection in RGMII/MII/RMII.
61 GNDD power_in Digital ground.
62 LED2_1 bidirectional Port 2 LED indicator 1; strap selects Port 5 GMII/MII MAC (PU, default) or PHY (PD) mode, and RMII clock mode (PU) or normal mode (PD).
63 LED2_0 bidirectional Port 2 LED indicator 0; strap enables REFCLKO 25 MHz output (PU, default) or disables it (PD).
64 LED1_1 bidirectional Port 1 LED indicator 1; strap selects PLL clock source: PU uses 25 MHz XI/XO, PD uses external TXC5 clock in Port 5 RMII normal mode.
65 LED1_0 bidirectional Port 1 LED indicator 0; strap selects 1Gbps (PU, default) or 10/100Mbps (PD) in GMII/RGMII.
66 SPIQ bidirectional SPI serial data output in slave mode; strap selects SPI slave mode (PD) or MDC/MDIO mode (PU), external resistor required.
67 SCL_MDC input Clock input for SPI (up to 50 MHz) or MDC/MDIO interface (up to 25 MHz).
68 SDA_MDIO bidirectional Serial data input in SPI slave mode, or MDC/MDIO data input/output.
69 SPIS_N input Active-low SPI slave chip select; when high the device is deselected and SPIQ is high impedance.
70 VDDIO power_in 3.3V, 2.5V or 1.8V digital VDD for digital I/O circuitry.
71 GNDD power_in Digital ground.
72 RST_N input Active-low hardware reset input.
73 VDD12D power_in 1.2V core power.
74 NC unconnected No connect.
75 ATST unconnected No connect; factory test pin.
76 VDDAT power_in 3.3V or 2.5V analog power.
77 ISET passive Transmit output current set; connect to GND through a 12.4 kΩ 1% resistor.
78 GNDA power_in Analog ground.
79 XI input Crystal/oscillator input for 25 MHz crystal or 3.3V oscillator, tolerance ±50 ppm.
80 XO output Crystal clock output, connected to one end of the 25 MHz crystal.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-80(10x10)
Category Interface ICs
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD12A, VDD12D (abs max) -0.5 1.8 V 112
Supply Voltage VDDAT, VDDIO (abs max) -0.5 4 V 112
Input Voltage (abs max) -0.5 4 V 112
Output Voltage (abs max) -0.5 4 V 112
Lead Temperature 260 °C soldering, 10s 112
Storage Temperature TS -55 150 °C 112
Maximum Junction Temperature 125 °C 112
ESD Rating 5 kV 112
Supply Voltage VDD12A, VDD12D 1.14 1.26 V 112
Supply Voltage VDDAT 3.135 3.465 V VDDAT @ 3.3V 112
Supply Voltage VDDAT 2.375 2.625 V VDDAT @ 2.5V 112
Supply Voltage VDDIO 3.135 3.465 V VDDIO @ 3.3V 112
Supply Voltage VDDIO 2.375 2.625 V VDDIO @ 2.5V 112
Supply Voltage VDDIO 1.71 1.89 V VDDIO @ 1.8V 112
Ambient Temperature Commercial TA 0 70 °C Commercial 112
Ambient Temperature Industrial TA -40 85 °C Industrial 112
Package Thermal Resistance ΘJA 55.05 °C/W No heat spreader, air velocity 0m/s 112
Package Thermal Resistance ΘJC 25.06 °C/W No heat spreader, air velocity 0m/s 112
Input High Voltage VIH 2 V VDDIO = 3.3V 113
Input High Voltage VIH 1.8 V VDDIO = 2.5V 113
Input High Voltage VIH 1.3 V VDDIO = 1.8V 113
Input Low Voltage VIL 0.8 V VDDIO = 3.3V 113
Input Low Voltage VIL 0.7 V VDDIO = 2.5V 113
Input Low Voltage VIL 0.5 V VDDIO = 1.8V 113
Input Current (Excluding Pull-Up/Pull-Down) IIN 10 µA VIN = GND ~ VDDIO 113
Output High Voltage VOH 2.4 V VDDIO = 3.3V 113
Output High Voltage VOH 2 V VDDIO = 2.5V 113
Output High Voltage VOH 1.5 V VDDIO = 1.8V 113
Output Low Voltage VOL 0.4 V VDDIO = 3.3V 114
Output Low Voltage VOL 0.3 V VDDIO = 1.8V 114
Output Tri-State Leakage IOZ 10 µA VIN = GND ~ VDDIO 114
100BASE-TX Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination on the differential output 114
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination on the differential output 114
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 114
100BASE-TX Rise/Fall Time Imbalance 0 0.5 ns 114
100BASE-TX Duty Cycle Distortion 0.5 ns printed as ±0.5 114
100BASE-TX Overshoot 5 % 114
100BASE-TX Output Jitters 0 0.75 1.4 ns Peak-to-Peak 114
10BASE-T Squelch Threshold VSQ 300 400 585 mV 5 MHz square wave 114
10BASE-T Peak Differential Output Voltage VP 2.2 2.5 2.8 V 100Ω termination on the differential output; VDDAT = 3.3V 114
10BASE-T Output Jitters 1.4 3.5 ns Peak-to-Peak; VDDAT = 3.3V 114
10BASE-T Rise/Fall Times 28 30 ns VDDAT = 3.3V 114
I/O Pin Effective Pull-Up Resistance R1.8PU 75 95 135 kΩ VDDIO = 1.8V 114
I/O Pin Effective Pull-Down Resistance R1.8PD 53 68 120 kΩ VDDIO = 1.8V 114
I/O Pin Effective Pull-Up Resistance R2.5PU 46 60 93 kΩ VDDIO = 2.5V 114
I/O Pin Effective Pull-Down Resistance R2.5PD 46 59 103 kΩ VDDIO = 2.5V 114
I/O Pin Effective Pull-Up Resistance R3.3PU 35 45 65 kΩ VDDIO = 3.3V 114
I/O Pin Effective Pull-Down Resistance R3.3PD 37 46 74 kΩ VDDIO = 3.3V 114
GMII Set-Up Time tIS 1.2 ns 115
GMII Hold Time tIH 1.2 ns 115
GMII Output Delay Respect to Clock Falling Edge tOD 1 ns 115
GMII Clock Cycle 8 ns 115
100BASE-TX Transmitter 3.3V Analog Current IDX 142 mA 100BASE-TX, all ports 100% utilization; VDDAT 113
100BASE-TX 1.2V Current ID12 35 mA 100BASE-TX, all ports 100% utilization; VDD12A + VDD12D 113
100BASE-TX Digital IO 3.3V Current IDDIO 15 mA 100BASE-TX, all ports 100% utilization; VDDIO 113
Soft Power-Down Mode 3.3V Current ISPDM1 0.07 mA VDDAT + VDDIO 113

CAD (KiCad official)

  • Symbol: KSZ8795CLXIC
  • Footprint: Package_QFP:LQFP-80_10x10mm_P0.4mm
  • 3D model: LQFP-80(10x10) (KiCad packages3D, STEP)
  • 3D model files: ksz8795clxic-etched.step / ksz8795clxic-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8795clxic.step / ksz8795clxic.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (132 pp, sha256 b0e475469d5538b8, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF