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KSZ8794CNXCC

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Microchip Tech Ethernet ICs, QFN-64-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icsksz8794cnxccfactory-2.0.0extractor-text

Changed since verified KSZ8794CNXCC

by Ray · last 30 Oct 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: KSZ8794CNXCC · QFN-64-EP(8x8) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 124-page datasheet
  • ✓distributor: lcsc C633468, digikey 576-4851-ND, mouser 998-KSZ8794CNXCC
  • ✓family: QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-b9830m2e/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! ksz8794cnxcc.kicad_sym✓ ksz8794cnxcc.kicad_mod✓ ksz8794cnxcc.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers ksz8794cnxcc: symbol repaired (body fitted to the names) · Ray 4d ago
ksz8794cnxcc-etched.glb Publish 0.1.0 · Ray 10d ago
ksz8794cnxcc-etched.step ksz8794cnxcc: factory component page (tier=mfr) · Ray 10d ago
ksz8794cnxcc-hero.glb ksz8794cnxcc: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
ksz8794cnxcc-hero.overlay.json Publish 0.1.0 · Ray 10d ago
ksz8794cnxcc.glb Publish 0.1.0 · Ray 10d ago
ksz8794cnxcc.kicad_mod Publish 0.1.0 · Ray 10d ago
ksz8794cnxcc.kicad_sym ksz8794cnxcc: symbol repaired (body fitted to the names) · Ray 4d ago
ksz8794cnxcc.lbr ksz8794cnxcc: symbol repaired (body fitted to the names) · Ray 4d ago
ksz8794cnxcc.step Publish 0.1.0 · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 65 pins · Ray 10d ago

KSZ8794CNXCC

Microchip Tech · Ethernet ICs · QFN-64-EP(8x8)

KSZ8794CNXCC from Microchip Tech, in a QFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD12A power_in 1.2V core power.
2 VDDAT power_in 3.3V or 2.5V analog power.
3 GNDA power_in Analog ground.
4 RXP1 input Port 1 physical receive signal + (differential).
5 RXM1 input Port 1 physical receive signal - (differential).
6 TXP1 output Port 1 physical transmit signal + (differential).
7 TXM1 output Port 1 physical transmit signal - (differential).
8 RXP2 input Port 2 physical receive signal + (differential).
9 RXM2 input Port 2 physical receive signal - (differential).
10 TXP2 output Port 2 physical transmit signal + (differential).
11 TXM2 output Port 2 physical transmit signal - (differential).
12 VDDAT power_in 3.3V or 2.5V analog power.
13 RXP3 input Port 3 physical receive signal + (differential).
14 RXM3 input Port 3 physical receive signal - (differential).
15 TXP3 output Port 3 physical transmit signal + (differential).
16 TXM3 output Port 3 physical transmit signal - (differential).
17 GNDA power_in Analog ground.
18 INTR_N output Active-low open-drain interrupt output; needs an external pull-up resistor when in use.
19 LED3_1 bidirectional Port 3 LED indicator 1 (internal pull-up during reset); strap with LED3_0 selects Port 4 GMAC4 mode: 00=MII, 01=RMII, 10=Reserved, 11=RGMII (default).
20 LED3_0 bidirectional Port 3 LED indicator 0 (internal pull-up during reset); strap option, see LED3_1 for GMAC4 interface mode select.
21 VDD12D power_in 1.2V core power.
22 GNDD power_in Digital ground.
23 TXEN4/TXD4_CTL input Port 4 transmit enable in MII/RMII, transmit data control in RGMII; internal pull-down.
24 TXD4_0 input Port 4 switch transmit bit [0] for RGMII/MII/RMII; internal pull-down.
25 TXD4_1 input Port 4 switch transmit bit [1] for RGMII/MII/RMII; internal pull-down.
26 GNDD power_in Digital ground.
27 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
28 TXD4_2 input Port 4 switch transmit bit [2] for RGMII/MII; no connection in RMII; internal pull-down.
29 TXD4_3 input Port 4 switch transmit bit [3] for RGMII/MII; no connection in RMII; internal pull-down.
30 TXER4 input Port 4 switch transmit error in MII; no connection in RGMII/RMII; internal pull-down.
31 NC unconnected No connect.
32 GNDD power_in Digital ground.
33 VDD12D power_in 1.2V core power.
34 TXC4/REFCLKI4/GTXC4 bidirectional Port 4 GMAC4 clock: MII 2.5/25 MHz (output in PHY mode, input in MAC mode), RMII 50 MHz clock input in normal mode, RGMII 125 MHz clock input.
35 RXC4/GRXC4 bidirectional Port 4 GMAC4 clock: MII 2.5/25 MHz (output in PHY mode, input in MAC mode), RMII 50 MHz reference clock output in clock mode, RGMII 125 MHz clock output.
36 RXD4_0 bidirectional Port 4 switch receive bit [0] for RGMII/MII/RMII; input with internal pull-down during reset, output otherwise.
37 RXD4_1 bidirectional Port 4 switch receive bit [1] for RGMII/MII/RMII; input with internal pull-down during reset, output otherwise.
38 GNDD power_in Digital ground.
39 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
40 RXD4_2 bidirectional Port 4 switch receive bit [2] for RGMII/MII; no connection in RMII; input with internal pull-down during reset, output otherwise.
41 RXD4_3 bidirectional Port 4 switch receive bit [3] for RGMII/MII; no connection in RMII; input with internal pull-down during reset, output otherwise.
42 RXDV4/CRSDV4/RXD4_CTL bidirectional Port 4 receive data valid (MII), carrier sense/receive data valid (RMII), or receive data control (RGMII); input with internal pull-down during reset, output otherwise.
43 RXER4 bidirectional Port 4 switch receive error in MII; no connection in RGMII/RMII; input with internal pull-down during reset, output otherwise.
44 CRS4 bidirectional Port 4 MII carrier sense; no connection in RGMII/RMII; input with internal pull-down during reset, output otherwise.
45 COL4 bidirectional Port 4 MII collision detect; no connection in RGMII/RMII; input with internal pull-down during reset, output otherwise.
46 REFCLKO bidirectional 25 MHz clock output (optional), enabled by default and controlled by strap pin LED2_0; better disabled if unused.
47 PME_N bidirectional Power management event signal indicating a Wake-on-LAN event was detected; polarity programmable, default active low.
48 LED2_1 bidirectional Port 2 LED indicator 1; strap selects Port 4 MII mode (PU=MAC, PD=PHY) or RMII mode (PU=clock mode providing 50 MHz from RXC4, PD=normal mode with external 50 MHz clock).
49 LED2_0 bidirectional Port 2 LED indicator 0; strap enables REFCLKO 25 MHz output (PU=enabled default, PD=disabled).
50 LED1_1 bidirectional Port 1 LED indicator 1; strap selects PLL clock source (PU=25 MHz XI/XO clock, PD=external clock from TXC4 in Port 4 RMII normal mode).
51 LED1_0 bidirectional Port 1 LED indicator 0; strap selects RGMII speed (PU=1 Gbps default, PD=10/100 Mbps).
52 SPIQ bidirectional SPI serial data output in SPI slave mode; strap selects serial bus (PD=SPI slave mode, PU=MDC/MDIO mode) and requires an external pull-up or pull-down resistor.
53 SCL_MDC input Clock for SPI (up to 50 MHz in SPI slave mode) or MDC/MDIO (up to 25 MHz) interfaces; internal pull-up.
54 SDA_MDIO bidirectional Serial data input in SPI slave mode or MDC/MDIO input/output data line.
55 SPIS_N input Active-low SPI chip select; when high the device is deselected and SPIQ is high impedance, a high-to-low transition starts SPI transfer.
56 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
57 GNDD power_in Digital ground.
58 RST_N input Active-low hardware reset with internal pull-up.
59 VDD12D power_in 1.2V core power.
60 VDDAT power_in 3.3V or 2.5V analog power.
61 ISET passive Transmit output current set; connect to GND through a 12.4 kΩ 1% resistor.
62 GNDA power_in Analog ground.
63 XI input Crystal/oscillator input; connect to a 25 MHz crystal or 3.3V oscillator output with ±50 ppm tolerance.
64 XO output Crystal clock output; connects to one end of the 25 MHz crystal circuit.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-64-EP(8x8)
Category Interface ICs
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD12A, VDD12D (abs max) -0.5 1.8 V VDD12A, VDD12D 106
Supply Voltage VDDAT, VDDIO (abs max) -0.5 4 V VDDAT, VDDIO 106
Input Voltage (abs max) -0.5 4 V 106
Output Voltage (abs max) -0.5 4 V 106
Lead Temperature 260 °C soldering, 10s 106
Storage Temperature TS -55 150 °C 106
Maximum Junction Temperature TJ 125 °C 106
ESD Rating (HBM) 5 kV HBM 106
Operating Supply Voltage VDD12A, VDD12D 1.14 1.26 V VDD12A, VDD12D 106
Operating Supply Voltage VDDAT @ 3.3V 3.135 3.465 V VDDAT @ 3.3V 106
Operating Supply Voltage VDDAT @ 2.5V 2.375 2.625 V VDDAT @ 2.5V 106
Operating Supply Voltage VDDIO @ 3.3V 3.135 3.465 V VDDIO @ 3.3V 106
Operating Supply Voltage VDDIO @ 2.5V 2.375 2.625 V VDDIO @ 2.5V 106
Operating Supply Voltage VDDIO @ 1.8V 1.71 1.89 V VDDIO @ 1.8V 106
Ambient Temperature (Commercial) TA 0 70 °C Commercial 106
Package Thermal Resistance ΘJA 31.96 °C/W Note 5-1: air velocity 0m/s, ePad 106
Package Thermal Resistance ΘJC 13.54 °C/W Note 5-1: air velocity 0m/s, ePad 106
Input High Voltage VIH 2 V VDDIO = 3.3V 107
Input High Voltage VIH 1.8 V VDDIO = 2.5V 107
Input High Voltage VIH 1.3 V VDDIO = 1.8V 107
Input Low Voltage VIL 0.8 V VDDIO = 3.3V 107
Input Low Voltage VIL 0.7 V VDDIO = 2.5V 107
Input Low Voltage VIL 0.5 V VDDIO = 1.8V 107
Input Current (Excluding Pull-Up/Pull-Down) IIN 10 µA VIN = GND ~ VDDIO 107
Output High Voltage VOH 2.4 V VDDIO = 3.3V 107
Output High Voltage VOH 2 V VDDIO = 2.5V 107
Output High Voltage VOH 1.5 V VDDIO = 1.8V 107
Output Low Voltage VOL 0.4 V VDDIO = 3.3V 108
Output Low Voltage VOL 0.3 V VDDIO = 1.8V 108
Output Tri-State Leakage IOZ 10 µA VIN = GND ~ VDDIO 108
100BASE-TX Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination on the differential output 108
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination on the differential output 108
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 108
100BASE-TX Rise/Fall Time Imbalance 0 0.5 ns 108
100BASE-TX Duty Cycle Distortion 0.5 ns ±0.5 ns 108
100BASE-TX Overshoot 5 % 108
100BASE-TX Output Jitters 0 0.75 1.4 ns Peak-to-Peak 108
10BASE-T Squelch Threshold VSQ 300 400 585 mV 5 MHz square wave 108
10BASE-T Peak Differential Output Voltage VP 2.2 2.5 2.8 V 100Ω termination on the differential output; VDDAT = 3.3V 108
10BASE-T Output Jitters 1.4 3.5 ns Peak-to-Peak; VDDAT = 3.3V 108
10BASE-T Rise/Fall Times 28 30 ns VDDAT = 3.3V 108
I/O Pin Effective Pull-Up Resistance R1.8PU 75 95 135 kΩ VDDIO = 1.8V 108
I/O Pin Effective Pull-Down Resistance R1.8PD 53 68 120 kΩ VDDIO = 1.8V 108
I/O Pin Effective Pull-Up Resistance R2.5PU 46 60 93 kΩ VDDIO = 2.5V 108
I/O Pin Effective Pull-Down Resistance R2.5PD 46 59 103 kΩ VDDIO = 2.5V 108
I/O Pin Effective Pull-Up Resistance R3.3PU 35 45 65 kΩ VDDIO = 3.3V 108
I/O Pin Effective Pull-Down Resistance R3.3PD 37 46 74 kΩ VDDIO = 3.3V 108
RGMII Data to clock output skew (transmitter) TskewT -500 0 500 ps Note 7-1 109
RGMII Data to clock input skew (receiver) TskewR 1 2.6 ns Note 7-1 109
RGMII Data to clock output setup (transmitter) TsetupT 1 2 ns integrated delay 109
RGMII Clock to data output hold (transmitter) TholdT 1 2 ns integrated delay 109
RGMII Data to clock input setup (receiver) TsetupR 0.8 2 ns integrated delay 109
RGMII Clock to data input hold (receiver) TholdR 0.8 2 ns integrated delay 109
RGMII Clock Cycle Duration Tcyc 7.2 8 8.8 ns Note 7-2 109
RGMII Duty Cycle for Gigabit Duty_G 45 50 55 % 109
RGMII Duty Cycle for 10/100T Duty_T 40 50 60 % 109
RGMII Rise/Fall Time (20-80%) tr/tf 0.75 ns 109
100BASE-TX 3.3V Analog Current IDX 107 mA 100BASE-TX, all ports 100% utilization, VDDAT 107
100BASE-TX 1.2V Current ID12 35 mA VDD12A + VDD12D 107
100BASE-TX Digital I/O 3.3V Current IDDIO 11 mA VDDIO 107

CAD (KiCad official)

  • Symbol: KSZ8794CNXCC
  • Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • 3D model: QFN-64-EP(8x8) (KiCad packages3D, STEP)
  • 3D model files: ksz8794cnxcc-etched.step / ksz8794cnxcc-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8794cnxcc.step / ksz8794cnxcc.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (124 pp, sha256 15cba2ada6d300b8, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF