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KSZ8794CNXCC-TR

Microchip Tech · Interface - Specialized · QFN-64-EP(8x8)

KSZ8794CNXCC-TR from Microchip Tech, in a QFN-64-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VDD12A	power_in	Supplies 1.2V core power.
2	VDDAT	power_in	Supplies 3.3V or 2.5V analog power.
3	GNDA	power_in	Analog ground.
4	RXP1	input	Port 1 physical receive signal + (differential).
5	RXM1	input	Port 1 physical receive signal - (differential).
6	TXP1	output	Port 1 physical transmit signal + (differential).
7	TXM1	output	Port 1 physical transmit signal - (differential).
8	RXP2	input	Port 2 physical receive signal + (differential).
9	RXM2	input	Port 2 physical receive signal - (differential).
10	TXP2	output	Port 2 physical transmit signal + (differential).
11	TXM2	output	Port 2 physical transmit signal - (differential).
12	VDDAT	power_in	Supplies 3.3V or 2.5V analog power.
13	RXP3	input	Port 3 physical receive signal + (differential).
14	RXM3	input	Port 3 physical receive signal - (differential).
15	TXP3	output	Port 3 physical transmit signal + (differential).
16	TXM3	output	Port 3 physical transmit signal - (differential).
17	GNDA	power_in	Analog ground.
18	INTR_N	output	Active-low interrupt open-drain output that requires an external pull-up resistor when used.
19	LED3_1	bidirectional	Port 3 LED indicator 1 (see Global Register 11 bits [5:4]), which also strap-selects the Port 4 GMAC4 mode via LED3[1:0] as 00=MII, 01=RMII, 10=Reserved, 11=RGMII (default).
20	LED3_0	bidirectional	Port 3 LED indicator 0 (see Global Register 11 bits [5:4]), which forms the LED3[1:0] Port 4 GMAC4 interface mode strap with LED3_1.
21	VDD12D	power_in	Supplies 1.2V core power.
22	GNDD	power_in	Digital ground.
23	TXEN4/TXD4_CTL	input	Port 4 switch transmit enable in MII/RMII modes or transmit data control in RGMII mode, with internal pull-down.
24	TXD4_0	input	Port 4 switch transmit bit 0 in RGMII/MII/RMII modes, with internal pull-down.
25	TXD4_1	input	Port 4 switch transmit bit 1 in RGMII/MII/RMII modes, with internal pull-down.
26	GNDD	power_in	Digital ground.
27	VDDIO	power_in	Supplies 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
28	TXD4_2	input	Port 4 switch transmit bit 2 in RGMII/MII modes with internal pull-down; no connection in RMII mode.
29	TXD4_3	input	Port 4 switch transmit bit 3 in RGMII/MII modes with internal pull-down; no connection in RMII mode.
30	TXER4	input	Port 4 switch MII transmit error with internal pull-down; no connection in RGMII/RMII modes.
31	NC	unconnected	No connect.
32	GNDD	power_in	Digital ground.
33	VDD12D	power_in	Supplies 1.2V core power.
34	TXC4/REFCLKI4/GTXC4	bidirectional	Port 4 GMAC4 transmit clock: 2.5/25 MHz in MII (output in PHY mode, input in MAC mode), 50 MHz input in RMII normal mode, and 125 MHz input in RGMII used to latch transmit data.
35	RXC4/GRXC4	bidirectional	Port 4 GMAC4 receive clock: 2.5/25 MHz in MII (output in PHY mode, input in MAC mode), 50 MHz reference clock output in RMII clock mode, and 125 MHz output in RGMII used to latch receive data.
36	RXD4_0	bidirectional	Port 4 switch receive bit 0 in RGMII/MII/RMII modes, with internal pull-down during reset and output pin otherwise.
37	RXD4_1	bidirectional	Port 4 switch receive bit 1 in RGMII/MII/RMII modes, with internal pull-down during reset and output pin otherwise.
38	GNDD	power_in	Digital ground.
39	VDDIO	power_in	Supplies 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
40	RXD4_2	bidirectional	Port 4 switch receive bit 2 in RGMII/MII modes with internal pull-down during reset; no connection in RMII mode.
41	RXD4_3	bidirectional	Port 4 switch receive bit 3 in RGMII/MII modes with internal pull-down during reset; no connection in RMII mode.
42	RXDV4/CRSDV4/RXD4_CTL	bidirectional	Port 4 MII receive data valid, RMII carrier sense/receive data valid output, or RGMII receive data control, with internal pull-down during reset.
43	RXER4	bidirectional	Port 4 switch MII receive error with internal pull-down during reset; no connection in RGMII/RMII modes.
44	CRS4	bidirectional	Port 4 switch MII carrier sense with internal pull-down during reset; no connection in RGMII/RMII modes.
45	COL4	bidirectional	Port 4 switch MII collision detect with internal pull-down during reset; no connection in RGMII/RMII modes.
46	REFCLKO	bidirectional	25 MHz clock output (optional) controlled by strap LED2_0, enabled by default and better disabled if not used.
47	PME_N	bidirectional	Power management event output that signals a Wake-On-LAN event, active low by default with programmable polarity.
48	LED2_1	bidirectional	Port 2 LED indicator 1 (see Global Register 11 bits [5:4]), which also strap-selects the Port 4 MII (MAC/PHY) or RMII (clock mode) operation.
49	LED2_0	bidirectional	Port 2 LED indicator 0 (see Global Register 11 bits [5:4]), which also strap-enables the 25 MHz REFCLKO output (pull-up enabled by default).
50	LED1_1	bidirectional	Port 1 LED indicator 1 (see Global Register 11 bits [5:4]), which also strap-selects the PLL clock source for Port 4 RMII normal mode.
51	LED1_0	bidirectional	Port 1 LED indicator 0 (see Global Register 11 bits [5:4]), which also strap-selects 1 Gbps (pull-up, default) or 10/100 Mbps (pull-down) RGMII speed.
52	SPIQ	bidirectional	SPI serial data output in SPI client mode, with the strap selecting SPI client mode (pull-down) or MDC/MDIO mode (pull-up) and requiring an external pull resistor.
53	SCL_MDC	input	Clock input for the SPI interface (up to 25 MHz in SPI client mode) or the MDC/MDIO interface (up to 25 MHz).
54	SDA_MDIO	bidirectional	Serial data line for SPI client mode (input) or the MDC/MDIO data input/output.
55	SPIS_N	input	Active-low SPI chip select where a high level deselects the device and tri-states SPIQ, and a high-to-low transition starts a SPI transfer.
56	VDDIO	power_in	Supplies 3.3V, 2.5V, or 1.8V digital VDD for digital I/O circuitry.
57	GNDD	power_in	Digital ground.
58	RST_N	input	Active-low hardware reset input; see the timing requirements in the Timing Diagram section.
59	VDD12D	power_in	Supplies 1.2V core power.
60	VDDAT	power_in	Supplies 3.3V or 2.5V analog power.
61	ISET	passive	Sets the transmit output current and must be connected to GND through a 12.4 kΩ 1% resistor.
62	GNDA	power_in	Analog ground.
63	XI	input	Crystal/oscillator input, connected to one end of a 25 MHz crystal or driven by a 3.3V oscillator, with ±50 ppm tolerance.
64	XO	output	Crystal clock output connected to the other end of the 25 MHz crystal circuit when a crystal is used.
65	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Microchip Tech
Package	QFN-64-EP(8x8)
Category	Interface
Pins	65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply Voltage (VDD12A, VDD12D)		-0.5		1.8	V		107
Supply Voltage (VDDAT, VDDIO)		-0.5		4	V		107
Input Voltage		-0.5		4	V		107
Output Voltage		-0.5		4	V		107
Lead Temperature (soldering, 10s)				260	°C	soldering, 10s	107
Storage Temperature (TS)	TS	-55		150	°C		107
Maximum Junction Temperature (TJ)	TJ			125	°C		107
ESD Rating (HBM)				5	kV	HBM	107
Supply Voltage (VDD12A, VDD12D)		1.14		1.26	V		107
Supply Voltage (VDDAT @ 3.3V)		3.135		3.465	V	VDDAT @ 3.3V	107
Supply Voltage (VDDAT @ 2.5V)		2.375		2.625	V	VDDAT @ 2.5V	107
Supply Voltage (VDDIO @ 3.3V)		3.135		3.465	V	VDDIO @ 3.3V	107
Supply Voltage (VDDIO @ 2.5V)		2.375		2.625	V	VDDIO @ 2.5V	107
Supply Voltage (VDDIO @ 1.8V)		1.71		1.89	V	VDDIO @ 1.8V	107
Ambient Temperature (TA) Commercial	TA	0		70	°C	Commercial	107
Ambient Temperature (TA) Industrial	TA	-40		85	°C	Industrial	107
Package Thermal Resistance (ΘJA)	ΘJA		31.96		°C/W	Air velocity 0 m/s; ePad under bottom of package (Note 5-1)	107
Package Thermal Resistance (ΘJC)	ΘJC		13.54		°C/W	Air velocity 0 m/s; ePad under bottom of package (Note 5-1)	107
CMOS Input High Voltage	VIH	2			V	VDDIO = 3.3V	108
CMOS Input High Voltage	VIH	1.8			V	VDDIO = 2.5V	108
CMOS Input High Voltage	VIH	1.3			V	VDDIO = 1.8V	108
CMOS Input Low Voltage	VIL			0.8	V	VDDIO = 3.3V	108
CMOS Input Low Voltage	VIL			0.7	V	VDDIO = 2.5V	108
CMOS Input Low Voltage	VIL			0.5	V	VDDIO = 1.8V	108
Input Current (Excluding Pull-Up/Pull-Down)	IIN			10	µA	VIN = GND ~ VDDIO	108
CMOS Output High Voltage	VOH	2.4			V	VDDIO = 3.3V	108
CMOS Output High Voltage	VOH	2			V	VDDIO = 2.5V	108
CMOS Output High Voltage	VOH	1.5			V	VDDIO = 1.8V	108
CMOS Output Low Voltage	VOL			0.4	V	VDDIO = 3.3V	109
CMOS Output Low Voltage	VOL			0.3	V	VDDIO = 1.8V	109
Output Tri-State Leakage	IOZ			10	µA	VIN = GND ~ VDDIO	109
Peak Differential Output Voltage (100BASE-TX)	VO	0.95		1.05	V	100Ω termination on the differential output	109
Output Voltage Imbalance	VIMB			2	%	100Ω termination on the differential output	109
Rise/Fall Time (100BASE-TX)	tr/tf	3		5	ns		109
Rise/Fall Time Imbalance		0		0.5			109
Duty Cycle Distortion		-0.5		0.5	ns		109
Overshoot				5	%		109
Output Jitters (100BASE-TX)				1.4	ns	Peak-to-Peak	109
10BASE-T Squelch Threshold	VSQ	300	400	585	mV	5 MHz square wave	109
10BASE-T Peak Differential Output Voltage	VP	2.2	2.5	2.8	V	VDDAT = 3.3V; 100Ω termination on the differential output	109
10BASE-T Output Jitters				3.5	ns	Peak-to-Peak	109
10BASE-T Rise/Fall Times				30	ns		109
I/O Pin Effective Pull-Up Resistance (VDDIO = 1.8V)	R1.8PU	75	95	135	kΩ	VDDIO = 1.8V	109
I/O Pin Effective Pull-Down Resistance (VDDIO = 1.8V)	R1.8PD	53	68	120	kΩ	VDDIO = 1.8V	109
I/O Pin Effective Pull-Up Resistance (VDDIO = 2.5V)	R2.5PU	46	60	93	kΩ	VDDIO = 2.5V	109
I/O Pin Effective Pull-Down Resistance (VDDIO = 2.5V)	R2.5PD	46	59	103	kΩ	VDDIO = 2.5V	109
I/O Pin Effective Pull-Up Resistance (VDDIO = 3.3V)	R3.3PU	35	45	65	kΩ	VDDIO = 3.3V	109
I/O Pin Effective Pull-Down Resistance (VDDIO = 3.3V)	R3.3PD	37	46	74	kΩ	VDDIO = 3.3V	109
Data to clock output skew (at transmitter)	TskewT	-500	0	500	ps		110
Data to clock input skew (at receiver)	TskewR	1		2.6	ns		110
Data to clock output setup (at transmitter, integrated delay)	TsetupT	1	2		ns		110
Clock to data output hold (at transmitter, integrated delay)	TholdT	1	2		ns		110
Data to clock input setup (at receiver, integrated delay)	TsetupR	0.8	2		ns		110
Clock to data input hold (at receiver, integrated delay)	TholdR	0.8	2		ns		110
Clock Cycle Duration	Tcyc	7.2	8	8.8	ns		110
Duty Cycle for Gigabit	Duty_G	45	50	55	%		110
Duty Cycle for 10/100T	Duty_T	40	50	60	%		110
Rise/Fall Time (20-80%)	tr/tf			0.75	ns	20-80%	110

CAD (KiCad official)

Symbol: KSZ8794CNXCC-TR
Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
3D model: QFN-64-EP(8x8) (KiCad packages3D, STEP)
3D model files: ksz8794cnxcc-tr-etched.step / ksz8794cnxcc-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8794cnxcc-tr.step / ksz8794cnxcc-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Microchip Tech datasheet (125 pp, sha256 d37034e2427691de, retrieved 2026-10-20, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF