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KSZ8563RNXV

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Microchip Tech Interface - Specialized, VQFN-64(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ksz8563rnxvfactory-2.0.0extractor-text

Verified KSZ8563RNXV

by Ray · last 31 Oct 2026 · 1 record · files match
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Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 65 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: KSZ8563RNXV · VQFN-64(8x8) · 65 pins
  • ✓copper: 65 copper pads, none touching another net
  • ✓datasheet: all 65 pin names found in the 221-page datasheet
  • ✓distributor: lcsc C3228581, digikey 150-KSZ8563RNXV-ND, mouser 579-KSZ8563RNXV
  • ✓family: QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-0an6resg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.213)
  • ✓pads: 65 pins = 65 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 65 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ksz8563rnxv.kicad_sym✓ ksz8563rnxv.kicad_mod✓ ksz8563rnxv.step
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Ray Publish 0.1.0 ac8f4f0 13h ago

KSZ8563RNXV

Microchip Tech · Interface - Specialized · VQFN-64(8x8)

KSZ8563RNXV from Microchip Tech, in a VQFN-64(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDDH power_in +3.3V / +2.5V analog power for the PHY transceivers and XI/XO crystal interface.
2 TX1P bidirectional Port 1 100BASE-TX/10BASE-T differential data (+); transmit in MDI mode, receive in MDI-X mode.
3 TX1M bidirectional Port 1 100BASE-TX/10BASE-T differential data (-); transmit in MDI mode, receive in MDI-X mode.
4 AVDDL power_in +1.2V analog power.
5 RX1P bidirectional Port 1 100BASE-TX/10BASE-T differential data (+); receive in MDI mode, transmit in MDI-X mode.
6 RX1M bidirectional Port 1 100BASE-TX/10BASE-T differential data (-); receive in MDI mode, transmit in MDI-X mode.
7 AVDDL power_in +1.2V analog power.
8 AVDDH power_in +3.3V / +2.5V analog power for the PHY transceivers and XI/XO crystal interface.
9 TX2P bidirectional Port 2 100BASE-TX/10BASE-T differential data (+); transmit in MDI mode, receive in MDI-X mode.
10 TX2M bidirectional Port 2 100BASE-TX/10BASE-T differential data (-); transmit in MDI mode, receive in MDI-X mode.
11 AVDDL power_in +1.2V analog power.
12 RX2P bidirectional Port 2 100BASE-TX/10BASE-T differential data (+); receive in MDI mode, transmit in MDI-X mode.
13 RX2M bidirectional Port 2 100BASE-TX/10BASE-T differential data (-); receive in MDI mode, transmit in MDI-X mode.
14 AVDDL power_in +1.2V analog power.
15 AVDDH power_in +3.3V / +2.5V analog power for the PHY transceivers and XI/XO crystal interface.
16 GND power_in Ground.
17 DVDDL power_in +1.2V digital power.
18 RXD3 bidirectional Port 3 receive data bit 3 in MII/RGMII modes (not used in RMII, do not connect); strap with RXD2 selects xMII mode (00 MII, 01 RMII, 11 RGMII).
19 RXD2 bidirectional Port 3 receive data bit 2 in MII/RGMII modes (not used in RMII, do not connect); strap with RXD3 selects xMII mode.
20 RXD1 bidirectional Port 3 receive data bit 1 in MII/RMII/RGMII modes; strap with RXD0 selects serial interface (00 MIIM, 01 I2C, 1x SPI).
21 RXD0 bidirectional Port 3 receive data bit 0 in MII/RMII/RGMII modes; strap with RXD1 selects serial interface mode.
22 RX_CLK/REFCLKO bidirectional MII: 25/2.5MHz receive clock (output in PHY mode, input in MAC mode); RMII: 50MHz reference clock output in Clock mode; RGMII: 125/25/2.5MHz receive clock output.
23 VDDIO power_in +3.3V / +2.5V / +1.8V digital I/O power.
24 RX_DV/CRS_DV/RX_CTL bidirectional Port 3 receive data valid (MII), carrier sense/receive data valid (RMII) or receive control (RGMII) output; strap selects Normal (0) or Factory Test (1) mode.
25 RX_ER bidirectional MII: Port 3 receive error output; not used in RMII/RGMII (do not connect); strap with PME_N sets port 1 and 2 PHY configuration.
26 TXD3 input Port 3 transmit data bit 3 in MII/RGMII modes; not used in RMII (do not connect).
27 TXD2 input Port 3 transmit data bit 2 in MII/RGMII modes; not used in RMII (do not connect).
28 TXD1 input Port 3 transmit data bit 1 in MII/RMII/RGMII modes.
29 TXD0 input Port 3 transmit data bit 0 in MII/RMII/RGMII modes.
30 TX_CLK/REFCLKI bidirectional MII: 25/2.5MHz transmit clock (output in PHY mode, input in MAC mode); RMII: 50MHz reference clock input in Normal mode; RGMII: 125/25/2.5MHz transmit clock input.
31 DVDDL power_in +1.2V digital power.
32 TX_EN/TX_CTL input Port 3 transmit enable in MII/RMII modes or transmit control in RGMII mode.
33 TX_ER input Port 3 transmit error input in MII mode; not used in RMII/RGMII (do not connect).
34 DVDDL power_in +1.2V digital power.
35 GND power_in Ground.
36 VDDIO power_in +3.3V / +2.5V / +1.8V digital I/O power.
37 GND power_in Ground.
38 VDDIO power_in +3.3V / +2.5V / +1.8V digital I/O power.
39 GND power_in Ground.
40 GPIO_1 bidirectional General purpose I/O synchronized to the IEEE 1588 clock; programmable as timestamp capture input or event trigger output.
41 GPIO_2 bidirectional General purpose I/O synchronized to the IEEE 1588 clock; programmable as timestamp capture input or event trigger output.
42 DVDDL power_in +1.2V digital power.
43 LED2_0 bidirectional Port 2 LED indicator 0, active-low output sinking current; strap selects Port 3 MII/RMII mode.
44 LED2_1 bidirectional Port 2 LED indicator 1, active-low output sinking current; strap selects Port 3 speed (0 = 1000Mbps, 1 = 100Mbps).
45 PME_N bidirectional Power management event output signalling an energy detect event, polarity programmable (default active low, external pull-up needed); strap with RX_ER sets PHY configuration.
46 INTRP_N output Active-low open-drain interrupt output; requires an external pull-up resistor.
47 RESET_N input Active-low system reset; the device must be reset during or after power-on, RC circuit suggested.
48 SDO bidirectional SPI data out (MISO), unused in I2C/MIIM modes; strap enables Quiet-WIRE filtering when 1.
49 SDI/SDA/MDIO bidirectional SPI data in, I2C SDA or MIIM MDIO; open-drain when outputting, needs 1.0kΩ to 5kΩ pull-up to VDDIO.
50 GND power_in Ground.
51 VDDIO power_in +3.3V / +2.5V / +1.8V digital I/O power.
52 SCS_N input SPI chip select, active low; unused in I2C/MIIM modes.
53 SCL/MDC input SCL serial clock in SPI/I2C modes or MDC serial clock in MIIM mode.
54 DVDDL power_in +1.2V digital power.
55 LED1_0 bidirectional Port 1 LED indicator 0, active-low output sinking current; strap enables switch at startup (1 default).
56 LED1_1 bidirectional Port 1 LED indicator 1, active-low output sinking current; strap disables (1, default) or enables (0) in-band management.
57 VDDIO power_in +3.3V / +2.5V / +1.8V digital I/O power.
58 GND power_in Ground.
59 DVDDL power_in +1.2V digital power.
60 AVDDL power_in +1.2V analog power.
61 XO output Crystal clock output; connects to one crystal lead for 25MHz crystal, left unconnected with an oscillator.
62 XI input Crystal/oscillator input for 25MHz clock, tolerance ±50ppm.
63 GND power_in Ground.
64 ISET passive Transmit output current set pin; must be connected to GND through a 6.04kΩ 1% resistor.
65 GND passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package VQFN-64(8x8)
Category Communication Interface Chip/UART/485/232
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage AVDDL, DVDDL (absolute max) AVDDL, DVDDL -0.5 1.8 V 192
Supply Voltage AVDDH, VDDIO (absolute max) AVDDH, VDDIO -0.5 5 V 192
Input Voltage (all inputs) -0.5 5 V 192
Output Voltage (all outputs) -0.5 5 V 192
Maximum current sunk/sourced by any I/O pin 50 mA 192
Lead Temperature 260 °C soldering, 10 sec. 192
Storage Temperature TS -55 150 °C 192
Maximum Junction Temperature TJ 125 °C 192
HBM ESD Performance -6 6 kV 192
Supply Voltage AVDDL, DVDDL AVDDL, DVDDL 1.14 1.26 V 192
Supply Voltage AVDDH @ 3.3V AVDDH 3.135 3.465 V AVDDH @ 3.3V 192
Supply Voltage AVDDH @ 2.5V AVDDH 2.375 2.625 V AVDDH @ 2.5V 192
Supply Voltage VDDIO @ 3.3V VDDIO 3.135 3.465 V VDDIO @ 3.3V 192
Supply Voltage VDDIO @ 2.5V VDDIO 2.375 2.625 V VDDIO @ 2.5V 192
Supply Voltage VDDIO @ 1.8V VDDIO 1.71 1.89 V VDDIO @ 1.8V 192
Ambient Operating Temperature (industrial version) TA -40 85 °C Still air, industrial version 192
Ambient Operating Temperature (automotive version) TA -40 105 °C Still air, Automotive version 192
Junction to Ambient Resistance θJA 22 °C/W 0 m/s air velocity 192
Junction to Case Characterization ΨJT 0.1 °C/W 0 m/s air velocity 192
Junction to Case Resistance θJC 1.3 °C/W 192
Input Current IIN -10 10 µA VIN = GND ~ VDDIO 193
Peak Differential Output Voltage (100BASE-TX) VO 0.95 1.05 V 100Ω termination on the differential output 194
Peak Differential Output Voltage (10BASE-T) Vp 2.2 2.5 2.8 V 100Ω termination on the differential output 194
Rise/Fall Time (100BASE-TX) tr, tf 3 5 ns 194
Output Jitter Peak-to-Peak (100BASE-TX) 0.7 1.4 ns 194
Jitter Added (10BASE-T) 1.8 3.5 ns 100Ω termination on the differential output (peak-to-peak) 194
Reference Voltage of ISET VSET 1.21 V using 6.04kΩ - 1% resistor 194
Squelch Threshold Vsq 400 mV 5MHz Square Wave 194
Clock cycle duration TCYC 7.2 8 8.8 ns RGMII 195
Data to clock output skew TSKEW 1.2 2 ns RGMII 195
Data to clock input setup TSETUP 1.1 ns RGMII 195
Data to clock input hold THOLD 0.9 ns RGMII 195
1000Mbps duty cycle Duty_G 45 50 55 % 195
10/100Mbps duty cycle Duty_T 40 50 60 % 195
Crystal frequency tolerance -50 50 ppm 25 MHz crystal 207
Crystal frequency 25 MHz 207

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs Quiet-WIRE is a feature to enhance 100BASE-TX EMC performance by reducing both conducted and radiated emis￾sions from the TXP/M signal pair. It can be used either to reduce absolute emissions, or to e 21

CAD (KiCad official)

  • Symbol: KSZ8563RNXV
  • Footprint: Package_DFN_QFN:QFN-64-1EP_8x8mm_P0.4mm_EP6.5x6.5mm
  • 3D model: VQFN-64(8x8) (KiCad packages3D, STEP)
  • 3D model files: ksz8563rnxv-etched.step / ksz8563rnxv-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8563rnxv.step / ksz8563rnxv.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (221 pp, sha256 94e5424ace3ec23c, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF