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KSZ8463FRLI

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Microchip Tech Interface - Specialized, LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentcommunication interface chip-uart-485-232ksz8463frlifactory-2.0.0extractor-text

Verified KSZ8463FRLI

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: KSZ8463FRLI · LQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 213-page datasheet
  • ✓distributor: lcsc C634203, digikey 576-4840-ND, mouser 998-KSZ8463FRLI
  • ✓family: LQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rmqtkdrq/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
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Verified files✓ ksz8463frli.kicad_sym✓ ksz8463frli.kicad_mod✓ ksz8463frli.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 6h ago
viewers ksz8463frli: viewers · Ray 6h ago
ksz8463frli-etched.glb Publish 0.1.0 · Ray 6h ago
ksz8463frli-etched.step ksz8463frli: factory component page (tier=mfr) · Ray 6h ago
ksz8463frli-hero.glb ksz8463frli: hero GLB from the etched model (keeps the MPN mark) · Ray 6h ago
ksz8463frli-hero.overlay.json Publish 0.1.0 · Ray 6h ago
ksz8463frli.glb Publish 0.1.0 · Ray 6h ago
ksz8463frli.kicad_mod Publish 0.1.0 · Ray 6h ago
ksz8463frli.kicad_sym Publish 0.1.0 · Ray 6h ago
ksz8463frli.lbr Publish 0.1.0 · Ray 6h ago
ksz8463frli.step Publish 0.1.0 · Ray 6h ago
package.json Publish 0.1.0 · Ray 6h ago
page.json Set visibility: public · Ray 6h ago
README.md Publish 0.1.0 · Ray 6h ago
verification.json Verified: Published by the parts factory: tier mfr, 64 pins · Ray 4h ago

KSZ8463FRLI

Microchip Tech · Interface - Specialized · LQFP-64(10x10)

KSZ8463FRLI from Microchip Tech, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 RXM1 bidirectional Port 1 physical receive (MDI) or transmit (MDIX) signal, negative differential.
2 RXP1 bidirectional Port 1 physical receive (MDI) or transmit (MDIX) signal, positive differential.
3 AGND power_in Analog ground.
4 TXM1 bidirectional Port 1 physical transmit (MDI) or receive (MDIX) signal, negative differential.
5 TXP1 bidirectional Port 1 physical transmit (MDI) or receive (MDIX) signal, positive differential.
6 VDD_AL power_in Low-voltage analog power input; its source should be filtered with a ferrite bead and capacitors.
7 ISET output Sets physical transmit output current; pull down with a 6.49 kΩ (1%) resistor to ground.
8 AGND power_in Analog ground.
9 VDD_A3.3 power_in 3.3V analog VDD input supply; must be well decoupled.
10 RXM2 bidirectional Port 2 physical receive (MDI) or transmit (MDIX) signal, negative differential.
11 RXP2 bidirectional Port 2 physical receive (MDI) or transmit (MDIX) signal, positive differential.
12 AGND power_in Analog ground.
13 TXM2 bidirectional Port 2 physical transmit (MDI) or receive (MDIX) signal, negative differential.
14 TXP2 bidirectional Port 2 physical transmit (MDI) or receive (MDIX) signal, positive differential.
15 FXSD2 input Port 2 fiber signal detect input in 100BASE-FX mode; in copper mode it is unused and should be pulled to GND.
16 VDD_COL power_in Second low-voltage analog power input, to be filtered with a ferrite bead and capacitors.
17 PWRDN input Active-low full-chip power-down with internal pull-up (low = power-down, high or floating = normal operation); all I/O pins are tri-stated while low.
18 X1 input 25 MHz crystal or oscillator clock connection (±50 ppm); with an oscillator, X1 connects to a VDD_IO-tolerant oscillator.
19 X2 output 25 MHz crystal connection; no connect when an oscillator is used on X1.
20 DGND power_in Digital ground.
21 VDD_IO power_in 3.3V, 2.5V, or 1.8V digital VDD input for IO logic and the internal low-voltage regulator.
22 TX_EN input RMII transmit enable, active high indicates valid transmit data on TXD[1:0]; internal pull-down.
23 TXD3/EN_REFCLKO input In RMII mode EN_REFCLKO enables the REFCLK_O output on pin 32 when pulled up and disables it when pulled down; internal pull-down.
24 TXD2/NC input No connect and not used in RMII mode (unused MII signals may be tied to ground via a resistor); internal pull-down.
25 TXD1 input RMII transmit data bit[1], synchronous to the 50 MHz REFCLK; internal pull-down.
26 TXD0 input RMII transmit data bit[0], synchronous to the 50 MHz REFCLK; internal pull-down.
27 TX_CLK/REFCLK_I input RMII 50 MHz reference input clock; internal pull-down.
28 TX_ER/MII_BP input No connect and not used in RMII mode per the pin table, though TX_ER may connect to the RMII PHY RX_ER; internal pull-down.
29 DGND power_in Digital ground.
30 VDD_IO power_in 3.3V, 2.5V, or 1.8V digital VDD input for IO logic and the internal low-voltage regulator.
31 RX_DV bidirectional RMII receive data valid, active high indicates valid data on RXD[1:0]; latched at power-up/reset as a PHY/MAC MII mode strap (pull-up default).
32 RXD3/REFCLK_O output RMII 50 MHz REFCLK_O output (16 mA drive) when EN_REFCLKO (pin 23) is pulled up; internal pull-down during reset.
33 RXD2 bidirectional Not used in RMII mode; at power-up/reset a pull-up (default) selects high-speed SPI (up to 50 MHz) and a pull-down selects low-speed SPI (up to 12.5 MHz).
34 RXD1 bidirectional RMII receive data bit[1], synchronous to REFCLK (50 MHz); latched at power-up/reset with RXD0 to select the serial bus mode.
35 RXD0 bidirectional RMII receive data bit[0], synchronous to REFCLK (50 MHz); latched at power-up/reset with RXD1 to select the serial bus mode.
36 CRS/GPIO9_RLI bidirectional GPIO9 in RMII mode; internal pull-down.
37 COL/GPIO10_RLI bidirectional GPIO10 in RMII mode; internal pull-down.
38 RX_CLK/GPIO7_RLI bidirectional GPIO7 in RMII mode; internal pull-down.
39 DGND power_in Digital ground.
40 VDD_L power_in Low-voltage input if the internal regulator is not used, or low-voltage output if the internal regulator is used.
41 SPI_DO bidirectional SPI slave serial data output; at power-up/reset a pull-up (default) selects the 25 MHz X1/X2 clock and a pull-down selects the 50 MHz REFCLK_I input.
42 SPI_CSN input Active-low SPI slave chip select with internal pull-down; needs an external 4.7 kΩ pull-up when in use.
43 INTRN output Active-low interrupt output to the host CPU; needs an external 4.7 kΩ pull-up resistor.
44 SPI_SCLK/MDC input Serial clock input in SPI slave mode, or MDC clock input in MIIM mode; internal pull-up.
45 SPI_DI/MDIO bidirectional SPI slave serial data input or MIIM MDIO data input/output; needs an external 4.7 kΩ pull-up resistor.
46 GPIO8 bidirectional General purpose I/O 8 with internal pull-down.
47 GPIO11 bidirectional General purpose I/O 11 with internal pull-up.
48 GPIO0 bidirectional General purpose I/O 0 usable by the IEEE 1588 event trigger or time stamp units, synchronized to the internal 1588 clock; internal pull-up.
49 GPIO1 bidirectional General purpose I/O 1 with internal pull-up.
50 DGND power_in Digital ground.
51 VDD_L power_in Low-voltage input if the internal regulator is not used, or low-voltage output if the internal regulator is used.
52 GPIO2 bidirectional General purpose I/O 2 with internal pull-up.
53 GPIO3 bidirectional General purpose I/O 3 with internal pull-down.
54 GPIO4 bidirectional General purpose I/O 4 with internal pull-down.
55 GPIO5 bidirectional General purpose I/O 5 with internal pull-down.
56 VDD_IO power_in 3.3V, 2.5V, or 1.8V digital VDD input for IO logic and the internal low-voltage regulator.
57 DGND power_in Digital ground.
58 GPIO6 bidirectional General purpose I/O 6 with internal pull-up.
59 P1LED1/GPIO7_MLI bidirectional Port 1 LED1 output in RMII mode, active (ON) when low.
60 P1LED0 bidirectional Port 1 LED0 output, active (ON) when low.
61 P2LED1/GPIO9_MLI bidirectional Port 2 LED1 output in RMII mode, active (ON) when low.
62 P2LED0/GPIO10_MLI bidirectional Port 2 LED0 output in RMII mode, active (ON) when low.
63 RSTN input Active-low hardware reset input with internal pull-up; must be low for at least 10 ms after VDD_IO and 3.3V supplies are stable.
64 FXSD1 input Port 1 fiber signal detect input in 100BASE-FX mode; in copper mode it is unused and should be pulled to GND.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package LQFP-64(10x10)
Category Communication Interface Chip/UART/485/232
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD_A3.3, VDD_IO (abs max) -0.5 5 V 189
Supply Voltage VDD_AL, VDD_L (abs max) -0.5 1.8 V 189
Input Voltage (All Inputs) -0.5 5 V 189
Output Voltage (All Outputs) -0.5 5 V 189
Lead Temperature (soldering, 10s) 260 °C soldering, 10s 189
Storage Temperature TS -65 150 °C 189
Maximum Junction Temperature TJ 125 °C 189
HBM ESD Rating 2 kV 189
Supply Voltage VDDA_3.3 VDDA_3.3 3.135 3.465 V 189
Supply Voltage VDD_L, VDD_AL, VDD_COL VDD_L 1.25 1.4 V 189
VDD_IO (3.3V) VDD_IO 3.135 3.465 V 3.3V 189
VDD_IO (2.5V) VDD_IO 2.375 2.625 V 2.5V 189
VDD_IO (1.8V) VDD_IO 1.71 1.89 V 1.8V 189
Ambient Operating Temperature (Industrial) TA -40 85 °C Industrial 189
Junction-to-Ambient ΘJA 49 °C/W No heat spreader, air velocity 0m/s 189
Junction-to-Case ΘJC 19 °C/W No heat spreader, air velocity 0m/s 189
CMOS Input Current IIN -10 10 µA VIN = GND ~ VDD_IO 191
X1 Input High Voltage VIH 2.1 V VDD_A3.3 = 3.3V, VDD_IO = any 191
X1 Input Low Voltage VIL 0.9 V VDD_A3.3 = 3.3V, VDD_IO = any 191
X1 Input Current IIN 10 µA 191
PWRDN Input High Voltage VIH 1.1 V VDD_A3.3 = 3.3V, VDD_IO = any 191
PWRDN Input Low Voltage VIL 0.3 V VDD_A3.3 = 3.3V, VDD_IO = any 192
FXSD Input High Voltage VIH 2.1 V VDD_A3.3 = 3.3V, VDD_IO = any 192
FXSD Input Low Voltage VIL 1.2 V VDD_A3.3 = 3.3V, VDD_IO = any 192
Output Tri-State Leakage /IOZ/ 10 µA 192
100BASE-TX Peak Differential Output Voltage VO -0.95 1.05 V 100Ω termination on the diff. output; printed ±0.95 to ±1.05 192
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination on the diff. output 192
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 192
Rise/Fall Time Imbalance 0 0.5 ns 192
Duty Cycle Distortion -0.25 0.25 ns 192
Overshoot 5 % 192
Output Jitter 0.7 1.4 ns Peak-to-peak 192
10BASE-T Transmit Peak Differential Output Voltage VP 2.2 2.5 2.8 V 100Ω termination on the differential output 192
10BASE-T Jitter Added 1.8 3.5 ns 100Ω termination on the differential output (peak-to-peak) 192
1.8V Pull-Up Resistance R1.8PU 57 100 187 kΩ VDD_IO = 1.8V 192
1.8V Pull-Down Resistance R1.8PD 55 100 190 kΩ VDD_IO = 1.8V 192
2.5V Pull-Up Resistance R2.5PU 37 59 102 kΩ VDD_IO = 2.5V 192
2.5V Pull-Down Resistance R2.5PD 35 60 110 kΩ VDD_IO = 2.5V 192
3.3V Pull-Up Resistance R3.3PU 29 43 70 kΩ VDD_IO = 3.3V 192
3.3V Pull-Down Resistance R3.3PD 27 43 76 kΩ VDD_IO = 3.3V 192
CMOS Input High Voltage (3.3V/2.5V/1.8V) VIH 2.1 V VDD_IO = 3.3V (2.1 / 1.7 / 1.3 for 3.3/2.5/1.8V) 191
CMOS Input Low Voltage (3.3V) VIL 0.9 V VDD_IO = 3.3V (0.9 / 0.9 / 0.6 for 3.3/2.5/1.8V) 191
CMOS Output High Voltage (3.3V) VOH 2.4 V IOH = -8 mA; VDD_IO = 3.3V (2.4 / 1.9 / 1.5 for 3.3/2.5/1.8V) 192
CMOS Output Low Voltage (3.3V) VOL 0.4 V IOL = 8 mA; VDD_IO = 3.3V (0.4 / 0.4 / 0.2 for 3.3/2.5/1.8V) 192
Internal LDO Output Voltage VLDO 1.32 V VDD_IO = 2.5V or 3.3V; internal regulator enabled; measured at pins 40 and 51 191
Reference Voltage of ISET VSET 0.65 V Using 6.49 kΩ, 1% resistor 192
10BASE-T Receive Squelch Threshold VSQ 400 mV 5 MHz square wave 192
LED Output Drive Current ILED 8 mA Each LED pin (P1/2LED0, P1/2LED1) 192
IVDD_A3.3, 100BASE-TX, regulator on IVDD_A3.3 46 mA 100% traffic on both ports 190
IVDD_IO, 100BASE-TX, regulator on IVDD_IO 98 mA 100% traffic on both ports 190
Device power dissipation, 100BASE-TX, regulator on PDISSDEVICE 476 mW 100% traffic on both ports 190
Device power dissipation, hardware power-down PDISSDEVICE 4.6 mW PWDRN pin held low 190
Reference crystal frequency tolerance -50 50 ppm 25 MHz crystal, maximum 205

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper In copper mode, and on the KSZ8463ML and KSZ8463RL, the FXSD pins are unused and should be pulled low. 18

CAD (KiCad official)

  • Symbol: KSZ8463FRLI
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: ksz8463frli-etched.step / ksz8463frli-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8463frli.step / ksz8463frli.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (213 pp, sha256 6e2255020c924402, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF