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KSZ8091RNDIA-TR

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Microchip Tech Ethernet Transceivers, QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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KSZ8091RNDIA-TR

Microchip Tech · Ethernet Transceivers · QFN-24-EP(4x4)

KSZ8091RNDIA-TR from Microchip Tech, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD_1.2 power_out The 1.2V core supply is generated by the device's internal regulator; decouple it with 2.2 µF and 0.1 µF capacitors to ground.
2 VDDA_3.3 power_in 3.3V analog VDD; connect to the board's 3.3V supply through a ferrite bead and decouple with 22 µF and 0.1 µF capacitors to ground.
3 RXM bidirectional Physical receive or transmit signal, negative (-) side of the differential copper pair.
4 RXP bidirectional Physical receive or transmit signal, positive (+) side of the differential copper pair.
5 TXM bidirectional Physical transmit or receive signal, negative (-) side of the differential copper pair.
6 TXP bidirectional Physical transmit or receive signal, positive (+) side of the differential copper pair.
7 XO output Crystal feedback for the 25 MHz crystal; leave as no connect when an oscillator or external clock source is used.
8 XI input Clock input: 25 MHz ±50 ppm crystal, oscillator or external clock in RMII 25 MHz mode, or 50 MHz ±50 ppm oscillator or clock in RMII 50 MHz mode.
9 REXT input Sets the PHY transmit output current; connect a 6.49 kΩ resistor to ground on this pin.
10 MDIO bidirectional MII management data I/O with a weak internal pull-up, open-drain output, requiring an external 1.0 kΩ pull-up resistor.
11 MDC input MII management clock input, synchronous to the MDIO data pin.
12 RXD1 output RMII receive data output bit 1, synchronous to the 50 MHz REF_CLK; internal pull-down during power-up/reset.
13 RXD0 output RMII receive data output bit 0, synchronous to the 50 MHz REF_CLK; internal pull-up during power-up/reset.
14 VDDIO power_in Digital I/O supply of 3.3V, 2.5V, or 1.8V; connect to the board supply for the chosen VDDIO and decouple with 22 µF and 0.1 µF capacitors to ground.
15 CRS_DV/PHYAD[1:0] output RMII carrier sense/receive data valid output; during reset it is a strap that latches PHY address 00011b (pull-up) or 00000b (pull-down, default) at reset de-assertion.
16 REF_CLK output Provides the 50 MHz RMII reference clock output to the MAC in RMII 25 MHz mode; it is a no connect in RMII 50 MHz mode.
17 RXER/PME_EN output RMII receive error output; during reset it is a strap that latches PME_EN, with pull-up enabling and pull-down (default) disabling the PME output for Wake-On-LAN.
18 INTRP/PME_N2 bidirectional Programmable interrupt output (active low by default) or PME_N Wake-On-LAN output; open-drain with weak pull-up, requiring an external 1.0 kΩ pull-up to VDDIO when used for interrupt or PME.
19 TXEN input RMII transmit enable input from the MAC, asserted with the first preamble dibit and negated before the first REF_CLK following the final dibit.
20 TXD0 input RMII transmit data input bit 0 from the MAC, accepted by the PHY when TXEN is asserted.
21 TXD1 bidirectional RMII transmit data input bit 1 from the MAC in normal operation; it is the NAND tree output in NAND tree test mode.
22 GND power_in Ground.
23 LED0/PME_N1/ANEN_SPEED output Programmable LED0 link/activity output, or PME_N1 Wake-On-LAN output (open-drain, requires 1.0 kΩ pull-up to VDDIO); at reset it latches auto-negotiation enable and speed (pull-up = enable AN and 100 Mbps, pull-down = 10 Mbps).
24 RST# input Active-low chip reset input with an internal pull-up.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-24-EP(4x4)
Category Interface
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VDD_1.2) VIN -0.5 1.8 V 45
Supply Voltage (VDDIO, VDDA_3.3) VIN -0.5 5 V 45
Input Voltage (all inputs) -0.5 5 V 45
Output Voltage (all outputs) -0.5 5 V 45
Storage Temperature TS -55 150 °C 45
Lead Temperature (soldering, 10s) 260 °C 45
Supply Voltage (VDDIO_3.3, VDDA_3.3) 3.135 3.465 V 45
Supply Voltage (VDDIO_2.5) 2.375 2.625 V 45
Supply Voltage (VDDIO_1.8) 1.71 1.89 V 45
Ambient Temperature (TA Industrial) TA -40 85 °C 45
Maximum Junction Temperature (TJ max.) TJ 125 °C 45
Input High Voltage VIH 2 V VDDIO = 3.3V 46
Input High Voltage VIH 1.8 V VDDIO = 2.5V 46
Input High Voltage VIH 1.3 V VDDIO = 1.8V 46
Input Low Voltage VIL 0.8 V VDDIO = 3.3V 46
Input Low Voltage VIL 0.7 V VDDIO = 2.5V 46
Input Low Voltage VIL 0.5 V VDDIO = 1.8V 46
Input Current /IIN/ 10 µA VIN = GND ~ VDDIO 46
Output High Voltage VOH 2.4 V VDDIO = 3.3V 46
Output High Voltage VOH 2 V VDDIO = 2.5V 46
Output High Voltage VOH 1.5 V VDDIO = 1.8V 46
Output Low Voltage VOL 0.4 V VDDIO = 3.3V 46
Output Low Voltage VOL 0.3 V VDDIO = 1.8V 46
Output Tri-State Leakage /IOZ/ 10 µA 46
Internal Pull-Up Resistance pu 30 45 73 kΩ VDDIO = 3.3V 46
Internal Pull-Up Resistance pu 39 61 102 kΩ VDDIO = 2.5V 46
Internal Pull-Up Resistance pu 48 99 178 kΩ VDDIO = 1.8V 46
Internal Pull-Down Resistance pd 26 43 79 kΩ VDDIO = 3.3V 46
Internal Pull-Down Resistance pd 34 59 113 kΩ VDDIO = 2.5V 46
Internal Pull-Down Resistance pd 53 99 200 kΩ VDDIO = 1.8V 46
Peak Differential Output Voltage (100BASE-TX) VO 0.95 1.05 V 100Ω termination across differential output 46
Output Voltage Imbalance (100BASE-TX) VIMB 2 % 100Ω termination across differential output 46
Rise/Fall Time (100BASE-TX) tr/tf 3 5 ns 46
Rise/Fall Time Imbalance (100BASE-TX) 0 0.5 ns 46
Duty Cycle Distortion (100BASE-TX) -0.25 0.25 ns 46
Overshoot (100BASE-TX) 5 % 46
Peak Differential Output Voltage (10BASE-T) VP 2.2 2.8 V 100Ω termination across differential output 47
Jitter Added (10BASE-T) 3.5 ns Peak-to-peak 47
Setup Time (25 MHz input to XI, 50 MHz REF_CLK output) t1 4 ns 25 MHz input to XI pin, 50 MHz output from REF_CLK pin 48
Hold Time (25 MHz input to XI, 50 MHz REF_CLK output) 2WH 2 ns 25 MHz input to XI pin, 50 MHz output from REF_CLK pin 48
Output Delay (25 MHz input to XI, 50 MHz REF_CLK output) tOD 7 10 13 ns 25 MHz input to XI pin, 50 MHz output from REF_CLK pin 48
Setup Time (50 MHz input to XI) t1 4 ns 50 MHz input to XI pin 48
Hold Time (50 MHz input to XI) 2WH 2 ns 50 MHz input to XI pin 48
Output Delay (50 MHz input to XI) tOD 8 11 13 ns 50 MHz input to XI pin 48
Thermal Resistance (ΘJA) ΘJA 49.22 °C/W 45
Thermal Resistance (ΘJC) ΘJC 25.65 °C/W 45

CAD (KiCad official)

  • Symbol: KSZ8091RNDIA-TR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ksz8091rndia-tr-etched.step / ksz8091rndia-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8091rndia-tr.step / ksz8091rndia-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (62 pp, sha256 c33fce4729df927d, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF