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KSZ8091RNBIA-TR

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Microchip Tech Ethernet Transceivers, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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KSZ8091RNBIA-TR

Microchip Tech · Ethernet Transceivers · QFN-32-EP(5x5)

KSZ8091RNBIA-TR from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground.
2 VDD_1.2 power_out 1.2V core VDD supplied by the KSZ8091RNB itself; decouple with 2.2 μF and 0.1 μF capacitors to ground.
3 VDDA_3.3 power_in 3.3V analog VDD.
4 RXM bidirectional Physical receive or transmit signal (- differential).
5 RXP bidirectional Physical receive or transmit signal (+ differential).
6 TXM bidirectional Physical transmit or receive signal (- differential).
7 TXP bidirectional Physical transmit or receive signal (+ differential).
8 XO output Crystal feedback for the 25 MHz crystal; this pin is a no connect if an oscillator or external clock source is used.
9 XI input 25 MHz mode: 25 MHz ±50 ppm crystal/oscillator/external clock input; 50 MHz mode: 50 MHz ±50 ppm oscillator/external clock input.
10 REXT input Sets the PHY transmit output current; connect a 6.49 kΩ resistor to ground on this pin.
11 MDIO bidirectional Management Interface (MII) data I/O; has a weak pull-up, is open-drain, and requires an external 1.0 kΩ pull-up resistor.
12 MDC input Management Interface (MII) clock input, synchronous to the MDIO data pin.
13 PHYAD0 bidirectional Pull-up/pull-down value is latched as PHYADDR[0] at de-assertion of reset.
14 PHYAD1 bidirectional Pull-up/pull-down value is latched as PHYADDR[1] at de-assertion of reset.
15 RXD1/PHYAD2 bidirectional RMII receive data output [1] in RMII mode; in config mode the pull-up/pull-down value is latched as PHYADDR[2] at de-assertion of reset.
16 RXD0/DUPLEX bidirectional RMII receive data output [0] in RMII mode; in config mode the pull-up/pull-down value is latched as DUPLEX at de-assertion of reset.
17 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD.
18 CRS_DV/CONFIG2 bidirectional RMII carrier sense/receive data valid output in RMII mode; in config mode the pull-up/pull-down value is latched as CONFIG2 at de-assertion of reset.
19 REF_CLK/B-CAST_OFF bidirectional In 25 MHz RMII mode this pin outputs the 50 MHz RMII reference clock to the MAC; in 50 MHz mode it is a no connect; in config mode it is latched as B-CAST_OFF at de-assertion of reset.
20 RXER/ISO bidirectional RMII receive error output in RMII mode; in config mode the pull-up/pull-down value is latched as ISOLATE at de-assertion of reset.
21 INTRP/PME_N2/NAND_Tree# bidirectional Programmable interrupt output (active low by default, set by Register 1Fh bit [9]) or PME_N output (pin option 2) asserted low on a WOL event; weak pull-up and open-drain, requiring an external 1.0 kΩ pull-up to VDDIO for interrupt and PME functions; latched as NAND Tree# at de-assertion of reset.
22 PME_EN bidirectional Pull-up/pull-down value is latched as PME_EN at de-assertion of reset.
23 TXEN input RMII transmit enable input.
24 TXD0 input RMII transmit data input [0], synchronous with the 50 MHz RMII reference clock and valid when TXEN is asserted.
25 TXD1 input RMII transmit data input [1], synchronous with the 50 MHz RMII reference clock and valid when TXEN is asserted.
26 NC unconnected No connect - this pin is not bonded and can be left floating.
27 NC unconnected No connect - this pin is not bonded and can be left floating.
28 CONFIG0 bidirectional Pull-up/pull-down value is latched as CONFIG0 at de-assertion of reset.
29 CONFIG1 bidirectional Pull-up/pull-down value is latched as CONFIG1 at de-assertion of reset.
30 LED0/PME_N1/NWAYEN bidirectional Programmable LED0 output; PME_N output (pin option 1) when enabled, open-drain with weak pull-up and requiring an external 1.0 kΩ pull-up to VDDIO; in config mode latched as auto-negotiation enable (Register 0h bit [12]) at de-assertion of reset.
31 LED1/SPEED bidirectional Programmable LED1 output; in config mode latched as SPEED (Register 0h bit [13]) at de-assertion of reset.
32 RST# input Chip reset, active low.
33 PADDLE passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Interface
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage (VIN) (VDD_1.2) VDD_1.2 -0.5 1.8 V 57
Supply Voltage (VDDIO, VDDA_3.3) VDDIO, VDDA_3.3 -0.5 5 V 57
Input Voltage (all inputs) -0.5 5 V 57
Output Voltage (all outputs) -0.5 5 V 57
Storage Temperature TS -55 150 °C 57
Lead Temperature 260 °C soldering, 10s 57
Supply Voltage (VDDIO_3.3, VDDA_3.3) VDDIO_3.3, VDDA_3.3 3.135 3.465 V 57
Supply Voltage (VDDIO_2.5) VDDIO_2.5 2.375 2.625 V 57
Supply Voltage (VDDIO_1.8) VDDIO_1.8 1.71 1.89 V 57
Ambient Temperature (TA Commercial) TA 0 70 °C 57
Ambient Temperature (TA Industrial) TA -40 85 °C 57
Maximum Junction Temperature (TJ max.) TJ 125 °C 57
Input High Voltage VIH 2 V VDDIO = 3.3V 58
Input High Voltage VIH 1.8 V VDDIO = 2.5V 58
Input High Voltage VIH 1.3 V VDDIO = 1.8V 58
Input Low Voltage VIL 0.8 V VDDIO = 3.3V 58
Input Low Voltage VIL 0.7 V VDDIO = 2.5V 58
Input Low Voltage VIL 0.5 V VDDIO = 1.8V 58
Input Current /IIN/ 10 μA VIN = GND ~ VDDIO 58
Output High Voltage VOH 2.4 V VDDIO = 3.3V 58
Output High Voltage VOH 2 V VDDIO = 2.5V 58
Output High Voltage VOH 1.5 V VDDIO = 1.8V 58
Output Low Voltage VOL 0.4 V VDDIO = 3.3V 58
Output Low Voltage VOL 0.3 V VDDIO = 1.8V 58
Output Tri-State Leakage /IOZ/ 10 μA 58
Internal Pull-Up Resistance Rpu 30 45 73 kΩ VDDIO = 3.3V 58
Internal Pull-Up Resistance Rpu 39 61 102 kΩ VDDIO = 2.5V 58
Internal Pull-Up Resistance Rpu 48 99 178 kΩ VDDIO = 1.8V 58
Internal Pull-Down Resistance Rpd 26 43 79 kΩ VDDIO = 3.3V 58
Internal Pull-Down Resistance Rpd 34 59 113 kΩ VDDIO = 2.5V 58
Internal Pull-Down Resistance Rpd 53 99 200 kΩ VDDIO = 1.8V 58
100BASE-TX Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination across differential output 58
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination across differential output 58
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 58
100BASE-TX Rise/Fall Time Imbalance 0 0.5 ns 58
100BASE-TX Duty Cycle Distortion -0.25 0.25 ns 58
100BASE-TX Overshoot 5 % 58
10BASE-T Peak Differential Output Voltage VP 2.2 2.8 V 100Ω termination across differential output 59
10BASE-T Jitter Added 3.5 ns Peak-to-peak 59
Thermal Resistance (ΘJA) ΘJA 45.87 °C/W 57
Thermal Resistance (ΘJC) ΘJC 15.85 °C/W 57

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing ppa 1 = RXC clock is stoppable for 100BASE-TX 52

CAD (KiCad official)

  • Symbol: KSZ8091RNBIA-TR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ksz8091rnbia-tr-etched.step / ksz8091rnbia-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8091rnbia-tr.step / ksz8091rnbia-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (80 pp, sha256 a7e3aab56aae2ff4, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF