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KSZ8091RNBCA

Public Made by Adom

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Microchip Tech Ethernet ICs, QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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KSZ8091RNBCA

Microchip Tech · Ethernet ICs · QFN-32-EP(5x5)

KSZ8091RNBCA from Microchip Tech, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground.
2 VDD_1.2 power_out 1.2V core VDD supplied by the KSZ8091RNB; decouple with 2.2 µF and 0.1 µF capacitors to ground.
3 VDDA_3.3 power_in 3.3V analog VDD; connect to the board 3.3V supply through a ferrite bead and decouple with 22 µF and 0.1 µF capacitors to ground.
4 RXM bidirectional Physical receive or transmit signal (- differential).
5 RXP bidirectional Physical receive or transmit signal (+ differential).
6 TXM bidirectional Physical transmit or receive signal (- differential).
7 TXP bidirectional Physical transmit or receive signal (+ differential).
8 XO output Crystal feedback for 25 MHz crystal; no connect if an oscillator or external clock source is used.
9 XI input Crystal/oscillator/external clock input: 25 MHz ±50 ppm in 25 MHz mode, 50 MHz ±50 ppm oscillator/external clock in 50 MHz mode.
10 REXT passive Sets PHY transmit output current; connect a 6.49 kΩ resistor to ground.
11 MDIO bidirectional Management interface data I/O with weak pull-up, open-drain, requires an external 1.0 kΩ pull-up resistor.
12 MDC input Management interface clock input with internal pull-up, synchronous to MDIO.
13 PHYAD0 bidirectional Pull-up/pull-down value is latched as PHYADDR[0] at de-assertion of reset (internal pull-up during reset).
14 PHYAD1 bidirectional Pull-up/pull-down value is latched as PHYADDR[1] at de-assertion of reset (internal pull-down during reset).
15 RXD1/PHYAD2 bidirectional RMII Receive Data output[1]; latched as PHYADDR[2] at de-assertion of reset (internal pull-down).
16 RXD0/DUPLEX bidirectional RMII Receive Data output[0]; latched as DUPLEX at de-assertion of reset (internal pull-up, default half-duplex).
17 VDDIO power_in 3.3V, 2.5V, or 1.8V digital VDD.
18 CRS_DV/CONFIG2 bidirectional RMII Carrier Sense/Receive Data Valid output; latched as CONFIG2 at de-assertion of reset (internal pull-down).
19 REF_CLK/B-CAST_OFF bidirectional Outputs the 50 MHz RMII reference clock in 25 MHz mode (no connect in 50 MHz mode); latched as B-CAST_OFF at de-assertion of reset (internal pull-down).
20 RXER/ISO bidirectional RMII Receive Error output; latched as ISOLATE at de-assertion of reset (internal pull-down).
21 INTRP/PME_N2/NAND_Tree# bidirectional Programmable interrupt (Reg 1Bh) or PME_N output, weak pull-up open-drain requiring external 1.0 kΩ pull-up to VDDIO; latched as NAND Tree# at de-assertion of reset.
22 PME_EN bidirectional Latched as PME_EN at de-assertion of reset (internal pull-down, default disabled).
23 TXEN input RMII Transmit Enable input.
24 TXD0 input RMII Transmit Data input[0].
25 TXD1 input RMII Transmit Data input[1].
26 NC unconnected No connect; pin is not bonded and can be left floating.
27 NC unconnected No connect; pin is not bonded and can be left floating.
28 CONFIG0 bidirectional Latched as CONFIG0 at de-assertion of reset (internal pull-down).
29 CONFIG1 bidirectional Latched as CONFIG1 at de-assertion of reset (internal pull-down); also NAND tree output.
30 LED0/PME_N1/NWAYEN bidirectional Programmable LED0 output or PME_N output (weak pull-up open-drain, external 1.0 kΩ pull-up to VDDIO); latched as auto-negotiation enable at de-assertion of reset.
31 LED1/SPEED bidirectional Programmable LED1 output; latched as SPEED (Register 0h bit 13) at de-assertion of reset (internal pull-up).
32 RST# input Chip reset, active low, with internal pull-up.
33 PADDLE power_in Exposed paddle on bottom of chip; ground.

Key specifications

Parameter Value
Manufacturer Microchip Tech
Package QFN-32-EP(5x5)
Category Interface ICs
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VDD_1.2 VIN -0.5 1.8 V VDD_1.2 57
Supply Voltage VDDIO, VDDA_3.3 VIN -0.5 5 V VDDIO, VDDA_3.3 57
Input Voltage (all inputs) -0.5 5 V all inputs 57
Output Voltage (all outputs) -0.5 5 V all outputs 57
Lead Temperature 260 °C soldering, 10s 57
Storage Temperature TS -55 150 °C 57
Supply Voltage 3.3V VDDIO_3.3, VDDA_3.3 3.135 3.465 V VDDIO_3.3, VDDA_3.3 57
Supply Voltage VDDIO 2.5V VDDIO_2.5 2.375 2.625 V 57
Supply Voltage VDDIO 1.8V VDDIO_1.8 1.71 1.89 V 57
Ambient Temperature Commercial TA 0 70 °C Commercial 57
Ambient Temperature Industrial TA -40 85 °C Industrial 57
Maximum Junction Temperature TJ max 125 °C 57
Thermal Resistance ΘJA 45.87 °C/W 57
Thermal Resistance ΘJC 15.85 °C/W 57
Input High Voltage VIH 2 V VDDIO = 3.3V 58
Input High Voltage VIH 1.8 V VDDIO = 2.5V 58
Input High Voltage VIH 1.3 V VDDIO = 1.8V 58
Input Low Voltage VIL 0.8 V VDDIO = 3.3V 58
Input Low Voltage VIL 0.7 V VDDIO = 2.5V 58
Input Low Voltage VIL 0.5 V VDDIO = 1.8V 58
Input Current /IIN/ 10 µA VIN = GND ~ VDDIO 58
Output High Voltage VOH 2.4 V VDDIO = 3.3V 58
Output High Voltage VOH 2 V VDDIO = 2.5V 58
Output High Voltage VOH 1.5 V VDDIO = 1.8V 58
Output Low Voltage VOL 0.4 V VDDIO = 3.3V 58
Output Low Voltage VOL 0.3 V VDDIO = 1.8V 58
Output Tri-State Leakage /IOZ/ 10 µA 58
Internal Pull-Up Resistance pu 30 45 73 kΩ VDDIO = 3.3V 58
Internal Pull-Up Resistance pu 39 61 102 kΩ VDDIO = 2.5V 58
Internal Pull-Up Resistance pu 48 99 178 kΩ VDDIO = 1.8V 58
Internal Pull-Down Resistance pd 26 43 79 kΩ VDDIO = 3.3V 58
Internal Pull-Down Resistance pd 34 59 113 kΩ VDDIO = 2.5V 58
Internal Pull-Down Resistance pd 53 99 200 kΩ VDDIO = 1.8V 58
100BASE-TX Peak Differential Output Voltage VO 0.95 1.05 V 100Ω termination across differential output 58
100BASE-TX Output Voltage Imbalance VIMB 2 % 100Ω termination across differential output 58
100BASE-TX Rise/Fall Time tr/tf 3 5 ns 58
100BASE-TX Rise/Fall Time Imbalance 0 0.5 ns 58
100BASE-TX Duty Cycle Distortion 0.25 ns printed ±0.25 58
100BASE-TX Overshoot 5 % 58
10BASE-T Peak Differential Output Voltage VP 2.2 2.8 V 100Ω termination across differential output 59
10BASE-T Jitter Added 3.5 ns Peak-to-peak 59
Supply Current 10BASE-T IDD1_3.3V 41 mA Full-duplex traffic @ 100% utilization 58
Supply Current 100BASE-TX IDD2_3.3V 47 mA Full-duplex traffic @ 100% utilization 58
Supply Current EEE (100 Mbps) IDD3_3.3V 23 mA TX and RX paths in LPI state with no traffic 58
Supply Current EDPD IDD4_3.3V 20 mA Ethernet cable disconnected (Reg. 18h.11 = 0) 58
Supply Current Power-Down IDD5_3.3V 4 mA Software power-down (Reg. 0h.11 = 1) 58
LED Output Drive Current ILED 8 mA Each LED pin (LED0, LED1) 58
Reference Voltage of ISET VSET 0.65 V R(ISET) = 6.49 kΩ 59
Squelch Threshold VSQ 400 mV 5 MHz square wave 59

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing ppa 1 = RXC clock is stoppable for 100BASE-TX 52

CAD (KiCad official)

  • Symbol: KSZ8091RNBCA
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: ksz8091rnbca-etched.step / ksz8091rnbca-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ksz8091rnbca.step / ksz8091rnbca.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip Tech datasheet (80 pp, sha256 861764ca6f1a2d5c, retrieved 2026-10-26, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF